f09678af51
I've noticed that PCI clock was incorrectly reported as 66 MHz while being
mere 33 MHz on RBTX4937 board -- this was due to the different encoding of
the PCI divisor field in CCFG register between TX4927 and TX4937 chips...
Also, RBTX49x7 was printed out as a CPU name (e.g., "CPU is RBTX4937");
and some debug printk() were duplicating each other...
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
286 lines
11 KiB
C
286 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*/
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#ifndef __ASM_TX4927_TX4927_PCI_H
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#define __ASM_TX4927_TX4927_PCI_H
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#define TX4927_CCFG_TOE 0x00004000
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#define TX4927_PCIMEM 0x08000000
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#define TX4927_PCIMEM_SIZE 0x08000000
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#define TX4927_PCIIO 0x16000000
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#define TX4927_PCIIO_SIZE 0x01000000
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#define TX4927_SDRAMC_REG 0xff1f8000
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#define TX4927_EBUSC_REG 0xff1f9000
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#define TX4927_PCIC_REG 0xff1fd000
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#define TX4927_CCFG_REG 0xff1fe000
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#define TX4927_IRC_REG 0xff1ff600
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#define TX4927_CE3 0x17f00000 /* 1M */
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#define TX4927_PCIRESET_ADDR 0xbc00f006
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#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
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#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
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#define tx4927_imstat_ptr(n) \
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((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
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/* bits for ISTAT3/IMASK3/IMSTAT3 */
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#define TX4927_INT3B_PCID 0
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#define TX4927_INT3B_PCIC 1
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#define TX4927_INT3B_PCIB 2
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#define TX4927_INT3B_PCIA 3
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#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
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#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
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#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
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#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
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/* bits for PCI_CLK (S6) */
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#define TX4927_PCI_CLK_HOST 0x80
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#define TX4927_PCI_CLK_MASK (0x0f << 3)
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#define TX4927_PCI_CLK_33 (0x01 << 3)
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#define TX4927_PCI_CLK_25 (0x04 << 3)
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#define TX4927_PCI_CLK_66 (0x09 << 3)
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#define TX4927_PCI_CLK_50 (0x0c << 3)
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#define TX4927_PCI_CLK_ACK 0x04
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#define TX4927_PCI_CLK_ACE 0x02
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#define TX4927_PCI_CLK_ENDIAN 0x01
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#define TX4927_NR_IRQ_LOCAL (8+16)
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#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
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#define TX4927_IR_PCIC 16
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#define TX4927_IR_PCIERR 22
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#define TX4927_IR_PCIPMA 23
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#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
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#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
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#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
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#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
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#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
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#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
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#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
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#ifdef _LANGUAGE_ASSEMBLY
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#define _CONST64(c) c
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#else
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#define _CONST64(c) c##ull
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#include <asm/byteorder.h>
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#define tx4927_pcireset_ptr \
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((volatile unsigned char *)TX4927_PCIRESET_ADDR)
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#define tx4927_pci_clk_ptr \
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((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
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struct tx4927_sdramc_reg {
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volatile unsigned long long cr[4];
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volatile unsigned long long unused0[4];
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volatile unsigned long long tr;
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volatile unsigned long long unused1[2];
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volatile unsigned long long cmd;
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};
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struct tx4927_ebusc_reg {
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volatile unsigned long long cr[8];
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};
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struct tx4927_ccfg_reg {
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volatile unsigned long long ccfg;
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volatile unsigned long long crir;
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volatile unsigned long long pcfg;
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volatile unsigned long long tear;
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volatile unsigned long long clkctr;
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volatile unsigned long long unused0;
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volatile unsigned long long garbc;
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volatile unsigned long long unused1;
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volatile unsigned long long unused2;
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volatile unsigned long long ramp;
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};
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struct tx4927_irc_reg {
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volatile unsigned long cer;
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volatile unsigned long cr[2];
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volatile unsigned long unused0;
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volatile unsigned long ilr[8];
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volatile unsigned long unused1[4];
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volatile unsigned long imr;
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volatile unsigned long unused2[7];
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volatile unsigned long scr;
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volatile unsigned long unused3[7];
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volatile unsigned long ssr;
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volatile unsigned long unused4[7];
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volatile unsigned long csr;
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};
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struct tx4927_pcic_reg {
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volatile unsigned long pciid;
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volatile unsigned long pcistatus;
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volatile unsigned long pciccrev;
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volatile unsigned long pcicfg1;
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volatile unsigned long p2gm0plbase; /* +10 */
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volatile unsigned long p2gm0pubase;
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volatile unsigned long p2gm1plbase;
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volatile unsigned long p2gm1pubase;
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volatile unsigned long p2gm2pbase; /* +20 */
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volatile unsigned long p2giopbase;
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volatile unsigned long unused0;
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volatile unsigned long pcisid;
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volatile unsigned long unused1; /* +30 */
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volatile unsigned long pcicapptr;
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volatile unsigned long unused2;
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volatile unsigned long pcicfg2;
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volatile unsigned long g2ptocnt; /* +40 */
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volatile unsigned long unused3[15];
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volatile unsigned long g2pstatus; /* +80 */
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volatile unsigned long g2pmask;
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volatile unsigned long pcisstatus;
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volatile unsigned long pcimask;
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volatile unsigned long p2gcfg; /* +90 */
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volatile unsigned long p2gstatus;
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volatile unsigned long p2gmask;
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volatile unsigned long p2gccmd;
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volatile unsigned long unused4[24]; /* +a0 */
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volatile unsigned long pbareqport; /* +100 */
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volatile unsigned long pbacfg;
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volatile unsigned long pbastatus;
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volatile unsigned long pbamask;
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volatile unsigned long pbabm; /* +110 */
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volatile unsigned long pbacreq;
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volatile unsigned long pbacgnt;
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volatile unsigned long pbacstate;
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volatile unsigned long long g2pmgbase[3]; /* +120 */
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volatile unsigned long long g2piogbase;
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volatile unsigned long g2pmmask[3]; /* +140 */
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volatile unsigned long g2piomask;
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volatile unsigned long long g2pmpbase[3]; /* +150 */
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volatile unsigned long long g2piopbase;
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volatile unsigned long pciccfg; /* +170 */
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volatile unsigned long pcicstatus;
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volatile unsigned long pcicmask;
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volatile unsigned long unused5;
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volatile unsigned long long p2gmgbase[3]; /* +180 */
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volatile unsigned long long p2giogbase;
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volatile unsigned long g2pcfgadrs; /* +1a0 */
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volatile unsigned long g2pcfgdata;
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volatile unsigned long unused6[8];
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volatile unsigned long g2pintack;
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volatile unsigned long g2pspc;
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volatile unsigned long unused7[12]; /* +1d0 */
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volatile unsigned long long pdmca; /* +200 */
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volatile unsigned long long pdmga;
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volatile unsigned long long pdmpa;
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volatile unsigned long long pdmcut;
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volatile unsigned long long pdmcnt; /* +220 */
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volatile unsigned long long pdmsts;
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volatile unsigned long long unused8[2];
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volatile unsigned long long pdmdb[4]; /* +240 */
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volatile unsigned long long pdmtdh; /* +260 */
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volatile unsigned long long pdmdms;
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};
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#endif /* _LANGUAGE_ASSEMBLY */
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/* IRCSR : Int. Current Status */
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#define TX4927_IRCSR_IF 0x00010000
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#define TX4927_IRCSR_ILV_MASK 0x00000700
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#define TX4927_IRCSR_IVL_MASK 0x0000001f
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/*
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* PCIC
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*/
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/* bits for G2PSTATUS/G2PMASK */
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#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
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#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
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#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
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/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
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#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
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/* bits for PBACFG */
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#define TX4927_PCIC_PBACFG_RPBA 0x00000004
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#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
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#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
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/* bits for G2PMnGBASE */
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#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
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/* bits for G2PIOGBASE */
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#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
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/* bits for PCICSTATUS/PCICMASK */
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#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
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/* bits for PCICCFG */
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#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
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#define TX4927_PCIC_PCICCFG_HRST 0x00000800
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#define TX4927_PCIC_PCICCFG_SRST 0x00000400
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#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
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#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
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#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
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#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
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#define TX4927_PCIC_PCICCFG_IISE 0x00000020
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#define TX4927_PCIC_PCICCFG_ATR 0x00000010
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#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
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/* bits for P2GMnGBASE */
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#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
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#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
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/* bits for P2GIOGBASE */
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#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
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#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
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#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
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#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
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#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
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/*
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* CCFG
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*/
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/* CCFG : Chip Configuration */
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#define TX4927_CCFG_PCI66 0x00800000
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#define TX4927_CCFG_PCIMIDE 0x00400000
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#define TX4927_CCFG_PCIXARB 0x00002000
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#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
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#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
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#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
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#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
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#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
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#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
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#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
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#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
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#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
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#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
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#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
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#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
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#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
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#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
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/* PCFG : Pin Configuration */
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#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
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#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
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/* CLKCTR : Clock Control */
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#define TX4927_CLKCTR_PCICKD 0x00400000
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#define TX4927_CLKCTR_PCIRST 0x00000040
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#ifndef _LANGUAGE_ASSEMBLY
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#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
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#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
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#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
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#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
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#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG)
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* __ASM_TX4927_TX4927_PCI_H */
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