041cb6241f
We were counting on the bootloader to init some stuff, like get the bus out of reset and enable accesses. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
292 lines
6.7 KiB
C
292 lines
6.7 KiB
C
/*
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* arch/ppc/syslib/mpc52xx_pci.c
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*
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* PCI code for the Freescale MPC52xx embedded CPU.
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*
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*
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* Maintainer : Sylvain Munaut <tnt@246tNt.com>
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/config.h>
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#include <asm/pci.h>
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#include <asm/mpc52xx.h>
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#include "mpc52xx_pci.h"
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#include <asm/delay.h>
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#include <asm/machdep.h>
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/* This macro is defined to activate the workaround for the bug
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435 of the MPC5200 (L25R). With it activated, we don't do any
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32 bits configuration access during type-1 cycles */
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#define MPC5200_BUG_435_WORKAROUND
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static int
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mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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u32 value;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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out_be32(hose->cfg_addr,
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(1 << 31) |
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((bus->number - hose->bus_offset) << 16) |
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(devfn << 8) |
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(offset & 0xfc));
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mb();
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#ifdef MPC5200_BUG_435_WORKAROUND
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if (bus->number != hose->bus_offset) {
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switch (len) {
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case 1:
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value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3));
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break;
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case 2:
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value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1));
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break;
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default:
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value = in_le16((u16 __iomem *)hose->cfg_data) |
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(in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
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break;
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}
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}
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else
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#endif
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{
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value = in_le32(hose->cfg_data);
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if (len != 4) {
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value >>= ((offset & 0x3) << 3);
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value &= 0xffffffff >> (32 - (len << 3));
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}
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}
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*val = value;
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out_be32(hose->cfg_addr, 0);
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mb();
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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u32 value, mask;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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out_be32(hose->cfg_addr,
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(1 << 31) |
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((bus->number - hose->bus_offset) << 16) |
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(devfn << 8) |
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(offset & 0xfc));
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mb();
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#ifdef MPC5200_BUG_435_WORKAROUND
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if (bus->number != hose->bus_offset) {
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switch (len) {
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case 1:
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out_8(((u8 __iomem *)hose->cfg_data) +
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(offset & 3), val);
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break;
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case 2:
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out_le16(((u16 __iomem *)hose->cfg_data) +
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((offset>>1) & 1), val);
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break;
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default:
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out_le16((u16 __iomem *)hose->cfg_data,
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(u16)val);
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out_le16(((u16 __iomem *)hose->cfg_data) + 1,
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(u16)(val>>16));
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break;
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}
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}
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else
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#endif
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{
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if (len != 4) {
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value = in_le32(hose->cfg_data);
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offset = (offset & 0x3) << 3;
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mask = (0xffffffff >> (32 - (len << 3)));
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mask <<= offset;
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value &= ~mask;
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val = value | ((val << offset) & mask);
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}
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out_le32(hose->cfg_data, val);
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}
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mb();
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out_be32(hose->cfg_addr, 0);
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mb();
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops mpc52xx_pci_ops = {
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.read = mpc52xx_pci_read_config,
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.write = mpc52xx_pci_write_config
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};
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static void __init
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mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
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{
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u32 tmp;
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/* Setup control regs */
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tmp = in_be32(&pci_regs->scr);
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tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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out_be32(&pci_regs->scr, tmp);
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/* Setup windows */
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out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
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MPC52xx_PCI_MEM_START + MPC52xx_PCI_MEM_OFFSET,
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MPC52xx_PCI_MEM_START,
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MPC52xx_PCI_MEM_SIZE ));
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out_be32(&pci_regs->iw1btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
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MPC52xx_PCI_MMIO_START + MPC52xx_PCI_MEM_OFFSET,
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MPC52xx_PCI_MMIO_START,
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MPC52xx_PCI_MMIO_SIZE ));
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out_be32(&pci_regs->iw2btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
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MPC52xx_PCI_IO_BASE,
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MPC52xx_PCI_IO_START,
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MPC52xx_PCI_IO_SIZE ));
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out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(
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( MPC52xx_PCI_IWCR_ENABLE | /* iw0btar */
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MPC52xx_PCI_IWCR_READ_MULTI |
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MPC52xx_PCI_IWCR_MEM ),
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( MPC52xx_PCI_IWCR_ENABLE | /* iw1btar */
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MPC52xx_PCI_IWCR_READ |
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MPC52xx_PCI_IWCR_MEM ),
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( MPC52xx_PCI_IWCR_ENABLE | /* iw2btar */
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MPC52xx_PCI_IWCR_IO )
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));
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out_be32(&pci_regs->tbatr0,
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MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
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out_be32(&pci_regs->tbatr1,
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MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
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out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
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/* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
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/* Not necessary and can be a bad thing if for example the bootloader
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is displaying a splash screen or ... Just left here for
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documentation purpose if anyone need it */
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tmp = in_be32(&pci_regs->gscr);
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#if 0
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out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
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udelay(50);
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#endif
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out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
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}
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static void
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mpc52xx_pci_fixup_resources(struct pci_dev *dev)
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{
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int i;
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/* We don't rely on boot loader for PCI and resets all
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devices */
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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struct resource *res = &dev->resource[i];
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if (res->end > res->start) { /* Only valid resources */
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res->end -= res->start;
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res->start = 0;
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res->flags |= IORESOURCE_UNSET;
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}
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}
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/* The PCI Host bridge of MPC52xx has a prefetch memory resource
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fixed to 1Gb. Doesn't fit in the resource system so we remove it */
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if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
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(dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200) ) {
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struct resource *res = &dev->resource[1];
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res->start = res->end = res->flags = 0;
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}
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}
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void __init
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mpc52xx_find_bridges(void)
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{
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struct mpc52xx_pci __iomem *pci_regs;
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struct pci_controller *hose;
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pci_assign_all_buses = 1;
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pci_regs = ioremap(MPC52xx_PA(MPC52xx_PCI_OFFSET), MPC52xx_PCI_SIZE);
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if (!pci_regs)
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return;
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hose = pcibios_alloc_controller();
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if (!hose) {
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iounmap(pci_regs);
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return;
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}
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->bus_offset = 0;
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hose->ops = &mpc52xx_pci_ops;
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mpc52xx_pci_setup(pci_regs);
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hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET;
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hose->io_base_virt = ioremap(MPC52xx_PCI_IO_BASE, MPC52xx_PCI_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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hose->cfg_addr = &pci_regs->car;
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hose->cfg_data = hose->io_base_virt;
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/* Setup resources */
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pci_init_resource(&hose->mem_resources[0],
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MPC52xx_PCI_MEM_START,
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MPC52xx_PCI_MEM_STOP,
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IORESOURCE_MEM|IORESOURCE_PREFETCH,
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"PCI prefetchable memory");
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pci_init_resource(&hose->mem_resources[1],
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MPC52xx_PCI_MMIO_START,
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MPC52xx_PCI_MMIO_STOP,
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IORESOURCE_MEM,
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"PCI memory");
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pci_init_resource(&hose->io_resource,
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MPC52xx_PCI_IO_START,
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MPC52xx_PCI_IO_STOP,
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IORESOURCE_IO,
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"PCI I/O");
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}
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