a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
114 lines
4.2 KiB
C
114 lines
4.2 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <mach/common.h>
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#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
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#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
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#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
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#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
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#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
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#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
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#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
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#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
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#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
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#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
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#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
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#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
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#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
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#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
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#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
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#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
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#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
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#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
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#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
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#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
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#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
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#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
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#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
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#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
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#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
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#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
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#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
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#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
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#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
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#define IIM_PROD_REV_SH 3
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#define IIM_PROD_REV_LEN 5
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/* Disable interrupt number "irq" in the AVIC */
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static void mxc_mask_irq(unsigned int irq)
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{
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__raw_writel(irq, AVIC_INTDISNUM);
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}
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/* Enable interrupt number "irq" in the AVIC */
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static void mxc_unmask_irq(unsigned int irq)
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{
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__raw_writel(irq, AVIC_INTENNUM);
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}
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static struct irq_chip mxc_avic_chip = {
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.ack = mxc_mask_irq,
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.mask = mxc_mask_irq,
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.unmask = mxc_unmask_irq,
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};
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/*
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* This function initializes the AVIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init mxc_init_irq(void)
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{
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int i;
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u32 reg;
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/* put the AVIC into the reset value with
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* all interrupts disabled
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*/
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__raw_writel(0, AVIC_INTCNTL);
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__raw_writel(0x1f, AVIC_NIMASK);
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/* disable all interrupts */
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__raw_writel(0, AVIC_INTENABLEH);
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__raw_writel(0, AVIC_INTENABLEL);
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/* all IRQ no FIQ */
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__raw_writel(0, AVIC_INTTYPEH);
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__raw_writel(0, AVIC_INTTYPEL);
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for (i = 0; i < MXC_MAX_INT_LINES; i++) {
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set_irq_chip(i, &mxc_avic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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/* Set WDOG2's interrupt the highest priority level (bit 28-31) */
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reg = __raw_readl(AVIC_NIPRIORITY6);
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reg |= (0xF << 28);
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__raw_writel(reg, AVIC_NIPRIORITY6);
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/* init architectures chained interrupt handler */
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mxc_register_gpios();
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printk(KERN_INFO "MXC IRQ initialized\n");
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}
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