6a0e243069
Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
94 lines
2.5 KiB
ArmAsm
94 lines
2.5 KiB
ArmAsm
/*
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* linux/arch/arm/mm/tlb-v6.S
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*
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* Copyright (C) 1997-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 6 TLB handling functions.
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* These assume a split I/D TLB.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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#define HARVARD_TLB
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/*
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* v6wbi_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*
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* It is assumed that:
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* - the "Invalidate single entry" instruction will invalidate
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* both the I and the D TLBs on Harvard-style TLBs
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*/
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ENTRY(v6wbi_flush_user_tlb_range)
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vma_vm_mm r3, r2 @ get vma->vm_mm
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mov ip, #0
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mmid r3, r3 @ get vm_mm->context.id
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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asid r3, r3 @ mask ASID
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orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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mov r1, r1, lsl #PAGE_SHIFT
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vma_vm_flags r2, r2 @ get vma->vm_flags
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1:
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#ifdef HARVARD_TLB
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
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tst r2, #VM_EXEC @ Executable area ?
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mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mov pc, lr
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/*
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* v6wbi_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(v6wbi_flush_kern_tlb_range)
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mov r2, #0
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mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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mov r0, r0, lsl #PAGE_SHIFT
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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#ifdef HARVARD_TLB
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
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mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
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mov pc, lr
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.section ".text.init", #alloc, #execinstr
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.type v6wbi_tlb_fns, #object
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ENTRY(v6wbi_tlb_fns)
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.long v6wbi_flush_user_tlb_range
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.long v6wbi_flush_kern_tlb_range
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.long v6wbi_tlb_flags
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.size v6wbi_tlb_fns, . - v6wbi_tlb_fns
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