08932d8196
Move the pinmux setting of the EP93xx GPIOs to the core code. This removes the need for the GPIO driver to have access to the system controller registers. Signed-off-by: Ryan Mallon <rmallon@gmail.com> Cc: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Hartley Sweeten <hsweeten@visionengravers.com>
420 lines
11 KiB
C
420 lines
11 KiB
C
/*
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* Generic EP93xx GPIO handling
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*
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* Copyright (c) 2008 Ryan Mallon
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* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
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*
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* Based on code originally from:
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* linux/arch/arm/mach-ep93xx/core.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/basic_mmio_gpio.h>
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#include <mach/hardware.h>
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#include <mach/gpio-ep93xx.h>
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#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
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struct ep93xx_gpio {
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void __iomem *mmio_base;
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struct bgpio_chip bgc[8];
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};
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/*************************************************************************
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* Interrupt handling for EP93xx on-chip GPIOs
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*************************************************************************/
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static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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static unsigned char gpio_int_debounce[3];
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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static void ep93xx_gpio_update_int_params(unsigned port)
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{
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BUG_ON(port > 2);
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__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
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__raw_writeb(gpio_int_type2[port],
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EP93XX_GPIO_REG(int_type2_register_offset[port]));
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__raw_writeb(gpio_int_type1[port],
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EP93XX_GPIO_REG(int_type1_register_offset[port]));
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__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
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EP93XX_GPIO_REG(int_en_register_offset[port]));
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}
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static inline void ep93xx_gpio_int_mask(unsigned line)
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{
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gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
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}
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static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (enable)
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gpio_int_debounce[port] |= port_mask;
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else
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gpio_int_debounce[port] &= ~port_mask;
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__raw_writeb(gpio_int_debounce[port],
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EP93XX_GPIO_REG(int_debounce_register_offset[port]));
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}
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static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned char status;
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int i;
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status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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}
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static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continuous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
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*/
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
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generic_handle_irq(gpio_irq);
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}
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static void ep93xx_gpio_irq_ack(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(port);
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}
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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gpio_int_unmasked[port] &= ~port_mask;
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ep93xx_gpio_update_int_params(port);
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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gpio_int_unmasked[port] &= ~(1 << (line & 7));
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ep93xx_gpio_update_int_params(port);
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}
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static void ep93xx_gpio_irq_unmask(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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gpio_int_unmasked[port] |= 1 << (line & 7);
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ep93xx_gpio_update_int_params(port);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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const int gpio = irq_to_gpio(d->irq);
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const int port = gpio >> 3;
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const int port_mask = 1 << (gpio & 7);
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irq_flow_handler_t handler;
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gpio_direction_input(gpio);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] |= port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] &= ~port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] |= port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] &= ~port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_int_type1[port] |= port_mask;
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/* set initial polarity based on current input level */
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if (gpio_get_value(gpio))
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gpio_int_type2[port] &= ~port_mask; /* falling */
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else
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gpio_int_type2[port] |= port_mask; /* rising */
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handler = handle_edge_irq;
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break;
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default:
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pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
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return -EINVAL;
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}
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__irq_set_handler_locked(d->irq, handler);
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gpio_int_enabled[port] |= port_mask;
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ep93xx_gpio_update_int_params(port);
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return 0;
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}
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static struct irq_chip ep93xx_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = ep93xx_gpio_irq_ack,
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.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
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.irq_mask = ep93xx_gpio_irq_mask,
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.irq_unmask = ep93xx_gpio_irq_unmask,
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.irq_set_type = ep93xx_gpio_irq_type,
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};
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static void ep93xx_gpio_init_irq(void)
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{
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int gpio_irq;
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for (gpio_irq = gpio_to_irq(0);
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gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
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irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(gpio_irq, IRQF_VALID);
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}
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irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
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ep93xx_gpio_ab_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
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ep93xx_gpio_f_irq_handler);
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}
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/*************************************************************************
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* gpiolib interface for EP93xx on-chip GPIOs
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*************************************************************************/
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struct ep93xx_gpio_bank {
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const char *label;
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int data;
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int dir;
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int base;
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bool has_debounce;
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};
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#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
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{ \
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.label = _label, \
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.data = _data, \
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.dir = _dir, \
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.base = _base, \
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.has_debounce = _debounce, \
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}
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static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
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EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
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EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
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EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
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EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
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EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
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EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
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EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
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EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
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};
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static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
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unsigned offset, unsigned debounce)
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{
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int gpio = chip->base + offset;
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int irq = gpio_to_irq(gpio);
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if (irq < 0)
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return -EINVAL;
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ep93xx_gpio_int_debounce(irq, debounce ? true : false);
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return 0;
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}
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/*
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* Map GPIO A0..A7 (0..7) to irq 64..71,
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* B0..B7 (7..15) to irq 72..79, and
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* F0..F7 (16..24) to irq 80..87.
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*/
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static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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int gpio = chip->base + offset;
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if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
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return -EINVAL;
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return 64 + gpio;
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}
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static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
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void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
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{
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void __iomem *data = mmio_base + bank->data;
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void __iomem *dir = mmio_base + bank->dir;
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int err;
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err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
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if (err)
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return err;
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bgc->gc.label = bank->label;
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bgc->gc.base = bank->base;
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if (bank->has_debounce) {
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bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
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bgc->gc.to_irq = ep93xx_gpio_to_irq;
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}
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return gpiochip_add(&bgc->gc);
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}
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static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
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{
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struct ep93xx_gpio *ep93xx_gpio;
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struct resource *res;
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void __iomem *mmio;
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int i;
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int ret;
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ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
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if (!ep93xx_gpio)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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ret = -ENXIO;
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goto exit_free;
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}
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if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
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ret = -EBUSY;
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goto exit_free;
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}
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mmio = ioremap(res->start, resource_size(res));
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if (!mmio) {
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ret = -ENXIO;
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goto exit_release;
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}
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ep93xx_gpio->mmio_base = mmio;
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
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struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
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struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
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if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
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dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
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bank->label);
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}
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ep93xx_gpio_init_irq();
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return 0;
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exit_release:
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release_mem_region(res->start, resource_size(res));
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exit_free:
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kfree(ep93xx_gpio);
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dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
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return ret;
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}
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static struct platform_driver ep93xx_gpio_driver = {
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.driver = {
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.name = "gpio-ep93xx",
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.owner = THIS_MODULE,
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},
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.probe = ep93xx_gpio_probe,
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};
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static int __init ep93xx_gpio_init(void)
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{
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return platform_driver_register(&ep93xx_gpio_driver);
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}
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postcore_initcall(ep93xx_gpio_init);
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MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
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"H Hartley Sweeten <hsweeten@visionengravers.com>");
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MODULE_DESCRIPTION("EP93XX GPIO driver");
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MODULE_LICENSE("GPL");
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