1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
52 lines
2.3 KiB
Plaintext
52 lines
2.3 KiB
Plaintext
README on the SDRAM Controller for the LH7a40X
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==============================================
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The standard configuration for the SDRAM controller generates a sparse
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memory array. The precise layout is determined by the SDRAM chips. A
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default kernel configuration assembles the discontiguous memory
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regions into separate memory nodes via the NUMA (Non-Uniform Memory
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Architecture) facilities. In this default configuration, the kernel
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is forgiving about the precise layout. As long as it is given an
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accurate picture of available memory by the bootloader the kernel will
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execute correctly.
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The SDRC supports a mode where some of the chip select lines are
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swapped in order to make SDRAM look like a synchronous ROM. Setting
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this bit means that the RAM will present as a contiguous array. Some
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programmers prefer this to the discontiguous layout. Be aware that
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may be a penalty for this feature where some some configurations of
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memory are significantly reduced; i.e. 64MiB of RAM appears as only 32
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MiB.
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There are a couple of configuration options to override the default
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behavior. When the SROMLL bit is set and memory appears as a
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contiguous array, there is no reason to support NUMA.
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CONFIG_LH7A40X_CONTIGMEM disables NUMA support. When physical memory
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is discontiguous, the memory tables are organized such that there are
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two banks per nodes with a small gap between them. This layout wastes
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some kernel memory for page tables representing non-existent memory.
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CONFIG_LH7A40X_ONE_BANK_PER_NODE optimizes the node tables such that
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there are no gaps. These options control the low level organization
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of the memory management tables in ways that may prevent the kernel
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from booting or may cause the kernel to allocated excessively large
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page tables. Be warned. Only change these options if you know what
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you are doing. The default behavior is a reasonable compromise that
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will suit all users.
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--
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A typical 32MiB system with the default configuration options will
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find physical memory managed as follows.
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node 0: 0xc0000000 4MiB
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0xc1000000 4MiB
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node 1: 0xc4000000 4MiB
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0xc5000000 4MiB
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node 2: 0xc8000000 4MiB
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0xc9000000 4MiB
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node 3: 0xcc000000 4MiB
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0xcd000000 4MiB
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Setting CONFIG_LH7A40X_ONE_BANK_PER_NODE will put each bank into a
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separate node.
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