3d64de9c50
The driver supports very simple GPIO controllers, that is, when a controller provides just a 'data' register. Such controllers may be found in various BCSRs (Board's FPGAs used to control board's switches, LEDs, chip-selects, Ethernet/USB PHY power, etc). So far we support only 1-byte GPIO banks. Support for other widths may be implemented when/if needed. p.s. To avoid "made up" compatible entries (like compatible = "simple-gpio"), boards must call simple_gpiochip_init() to pass the compatible string. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
156 lines
3.3 KiB
C
156 lines
3.3 KiB
C
/*
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* Simple Memory-Mapped GPIOs
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*
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* Copyright (c) MontaVista Software, Inc. 2008.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <asm/prom.h>
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#include "simple_gpio.h"
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struct u8_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/* shadowed data register to clear/set bits safely */
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u8 data;
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};
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static struct u8_gpio_chip *to_u8_gpio_chip(struct of_mm_gpio_chip *mm_gc)
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{
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return container_of(mm_gc, struct u8_gpio_chip, mm_gc);
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}
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static u8 u8_pin2mask(unsigned int pin)
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{
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return 1 << (8 - 1 - pin);
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}
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static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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return in_8(mm_gc->regs) & u8_pin2mask(gpio);
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}
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static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
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unsigned long flags;
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spin_lock_irqsave(&u8_gc->lock, flags);
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if (val)
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u8_gc->data |= u8_pin2mask(gpio);
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else
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u8_gc->data &= ~u8_pin2mask(gpio);
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out_8(mm_gc->regs, u8_gc->data);
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spin_unlock_irqrestore(&u8_gc->lock, flags);
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}
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static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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return 0;
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}
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static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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u8_gpio_set(gc, gpio, val);
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return 0;
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}
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static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
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u8_gc->data = in_8(mm_gc->regs);
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}
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static int __init u8_simple_gpiochip_add(struct device_node *np)
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{
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int ret;
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struct u8_gpio_chip *u8_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct of_gpio_chip *of_gc;
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struct gpio_chip *gc;
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u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
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if (!u8_gc)
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return -ENOMEM;
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spin_lock_init(&u8_gc->lock);
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mm_gc = &u8_gc->mm_gc;
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of_gc = &mm_gc->of_gc;
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gc = &of_gc->gc;
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mm_gc->save_regs = u8_gpio_save_regs;
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of_gc->gpio_cells = 2;
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gc->ngpio = 8;
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gc->direction_input = u8_gpio_dir_in;
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gc->direction_output = u8_gpio_dir_out;
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gc->get = u8_gpio_get;
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gc->set = u8_gpio_set;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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return 0;
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err:
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kfree(u8_gc);
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return ret;
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}
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void __init simple_gpiochip_init(const char *compatible)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, compatible) {
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int ret;
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struct resource r;
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ret = of_address_to_resource(np, 0, &r);
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if (ret)
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goto err;
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switch (resource_size(&r)) {
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case 1:
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ret = u8_simple_gpiochip_add(np);
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if (ret)
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goto err;
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break;
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default:
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/*
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* Whenever you need support for GPIO bank width > 1,
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* please just turn u8_ code into huge macros, and
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* construct needed uX_ code with it.
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*/
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ret = -ENOSYS;
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goto err;
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}
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continue;
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err:
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pr_err("%s: registration failed, status %d\n",
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np->full_name, ret);
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}
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}
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