712 lines
18 KiB
C
712 lines
18 KiB
C
/*
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* pata_amd.c - AMD PATA for new ATA layer
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* (C) 2005-2006 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based on pata-sil680. Errata information is taken from data sheets
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* and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
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* claimed by sata-nv.c.
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*
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* TODO:
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* Variable system clock when/if it makes sense
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* Power management on ports
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*
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*
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* Documentation publically available.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_amd"
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#define DRV_VERSION "0.2.4"
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/**
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* timing_setup - shared timing computation and load
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* @ap: ATA port being set up
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* @adev: drive being configured
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* @offset: port offset
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* @speed: target speed
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* @clock: clock multiplier (number of times 33MHz for this part)
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*
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* Perform the actual timing set up for Nvidia or AMD PATA devices.
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* The actual devices vary so they all call into this helper function
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* providing the clock multipler and offset (because AMD and Nvidia put
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* the ports at different locations).
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*/
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static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
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{
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static const unsigned char amd_cyc2udma[] = {
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6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct ata_device *peer = ata_dev_pair(adev);
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int dn = ap->port_no * 2 + adev->devno;
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struct ata_timing at, apeer;
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int T, UT;
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const int amd_clock = 33333; /* KHz. */
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u8 t;
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T = 1000000000 / amd_clock;
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UT = T / min_t(int, max_t(int, clock, 1), 2);
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if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
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dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
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return;
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}
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if (peer) {
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/* This may be over conservative */
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if (peer->dma_mode) {
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ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
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ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
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}
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ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
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ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
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}
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if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
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if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
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/*
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* Now do the setup work
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*/
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/* Configure the address set up timing */
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pci_read_config_byte(pdev, offset + 0x0C, &t);
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t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
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pci_write_config_byte(pdev, offset + 0x0C , t);
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/* Configure the 8bit I/O timing */
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pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
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((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
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/* Drive timing */
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pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
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((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
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switch (clock) {
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case 1:
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t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
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break;
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case 2:
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t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
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break;
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case 3:
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t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
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break;
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case 4:
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t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
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break;
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default:
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return;
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}
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/* UDMA timing */
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pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
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}
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/**
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* amd_probe_init - cable detection
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* @ap: ATA port
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*
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* Perform cable detection. The BIOS stores this in PCI config
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* space for us.
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*/
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static int amd_pre_reset(struct ata_port *ap)
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{
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static const u32 bitmask[2] = {0x03, 0xC0};
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static const struct pci_bits amd_enable_bits[] = {
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{ 0x40, 1, 0x02, 0x02 },
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{ 0x40, 1, 0x01, 0x01 }
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ata66;
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if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
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return -ENOENT;
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pci_read_config_byte(pdev, 0x42, &ata66);
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if (ata66 & bitmask[ap->port_no])
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ap->cbl = ATA_CBL_PATA80;
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else
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ap->cbl = ATA_CBL_PATA40;
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return ata_std_prereset(ap);
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}
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static void amd_error_handler(struct ata_port *ap)
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{
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return ata_bmdma_drive_eh(ap, amd_pre_reset,
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ata_std_softreset, NULL,
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ata_std_postreset);
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}
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static int amd_early_pre_reset(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static struct pci_bits amd_enable_bits[] = {
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{ 0x40, 1, 0x02, 0x02 },
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{ 0x40, 1, 0x01, 0x01 }
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};
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if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
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return -ENOENT;
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/* No host side cable detection */
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ap->cbl = ATA_CBL_PATA80;
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return ata_std_prereset(ap);
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}
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static void amd_early_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, amd_early_pre_reset,
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ata_std_softreset, NULL,
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ata_std_postreset);
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}
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/**
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* amd33_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the AMD registers for PIO mode.
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*/
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static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
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}
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static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
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}
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static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
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}
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static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
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}
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/**
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* amd33_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the MWDMA/UDMA modes for the AMD and Nvidia
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* chipset.
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*/
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static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
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}
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static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
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}
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static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
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}
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static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
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}
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/**
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* nv_probe_init - cable detection
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* @ap: ATA port
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*
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* Perform cable detection. The BIOS stores this in PCI config
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* space for us.
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*/
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static int nv_pre_reset(struct ata_port *ap) {
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static const u8 bitmask[2] = {0x03, 0xC0};
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static const struct pci_bits nv_enable_bits[] = {
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{ 0x50, 1, 0x02, 0x02 },
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{ 0x50, 1, 0x01, 0x01 }
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ata66;
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u16 udma;
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if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
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return -ENOENT;
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pci_read_config_byte(pdev, 0x52, &ata66);
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if (ata66 & bitmask[ap->port_no])
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ap->cbl = ATA_CBL_PATA80;
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else
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ap->cbl = ATA_CBL_PATA40;
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/* We now have to double check because the Nvidia boxes BIOS
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doesn't always set the cable bits but does set mode bits */
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pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
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if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
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ap->cbl = ATA_CBL_PATA80;
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return ata_std_prereset(ap);
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}
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static void nv_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, nv_pre_reset,
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ata_std_softreset, NULL,
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ata_std_postreset);
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}
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/**
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* nv100_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the AMD registers for PIO mode.
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*/
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static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
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}
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static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
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}
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/**
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* nv100_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the MWDMA/UDMA modes for the AMD and Nvidia
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* chipset.
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*/
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static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
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}
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static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
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}
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static struct scsi_host_template amd_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations amd33_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = amd33_set_piomode,
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.set_dmamode = amd33_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = amd_early_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static struct ata_port_operations amd66_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = amd66_set_piomode,
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.set_dmamode = amd66_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = amd_early_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static struct ata_port_operations amd100_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = amd100_set_piomode,
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.set_dmamode = amd100_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = amd_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static struct ata_port_operations amd133_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = amd133_set_piomode,
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.set_dmamode = amd133_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = amd_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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|
|
.port_start = ata_port_start,
|
|
.port_stop = ata_port_stop,
|
|
.host_stop = ata_host_stop
|
|
};
|
|
|
|
static struct ata_port_operations nv100_port_ops = {
|
|
.port_disable = ata_port_disable,
|
|
.set_piomode = nv100_set_piomode,
|
|
.set_dmamode = nv100_set_dmamode,
|
|
.mode_filter = ata_pci_default_filter,
|
|
.tf_load = ata_tf_load,
|
|
.tf_read = ata_tf_read,
|
|
.check_status = ata_check_status,
|
|
.exec_command = ata_exec_command,
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
.freeze = ata_bmdma_freeze,
|
|
.thaw = ata_bmdma_thaw,
|
|
.error_handler = nv_error_handler,
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
.bmdma_start = ata_bmdma_start,
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
.bmdma_status = ata_bmdma_status,
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
.qc_issue = ata_qc_issue_prot,
|
|
|
|
.data_xfer = ata_pio_data_xfer,
|
|
|
|
.irq_handler = ata_interrupt,
|
|
.irq_clear = ata_bmdma_irq_clear,
|
|
|
|
.port_start = ata_port_start,
|
|
.port_stop = ata_port_stop,
|
|
.host_stop = ata_host_stop
|
|
};
|
|
|
|
static struct ata_port_operations nv133_port_ops = {
|
|
.port_disable = ata_port_disable,
|
|
.set_piomode = nv133_set_piomode,
|
|
.set_dmamode = nv133_set_dmamode,
|
|
.mode_filter = ata_pci_default_filter,
|
|
.tf_load = ata_tf_load,
|
|
.tf_read = ata_tf_read,
|
|
.check_status = ata_check_status,
|
|
.exec_command = ata_exec_command,
|
|
.dev_select = ata_std_dev_select,
|
|
|
|
.freeze = ata_bmdma_freeze,
|
|
.thaw = ata_bmdma_thaw,
|
|
.error_handler = nv_error_handler,
|
|
.post_internal_cmd = ata_bmdma_post_internal_cmd,
|
|
|
|
.bmdma_setup = ata_bmdma_setup,
|
|
.bmdma_start = ata_bmdma_start,
|
|
.bmdma_stop = ata_bmdma_stop,
|
|
.bmdma_status = ata_bmdma_status,
|
|
|
|
.qc_prep = ata_qc_prep,
|
|
.qc_issue = ata_qc_issue_prot,
|
|
|
|
.data_xfer = ata_pio_data_xfer,
|
|
|
|
.irq_handler = ata_interrupt,
|
|
.irq_clear = ata_bmdma_irq_clear,
|
|
|
|
.port_start = ata_port_start,
|
|
.port_stop = ata_port_stop,
|
|
.host_stop = ata_host_stop
|
|
};
|
|
|
|
static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
static struct ata_port_info info[10] = {
|
|
{ /* 0: AMD 7401 */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07, /* No SWDMA */
|
|
.udma_mask = 0x07, /* UDMA 33 */
|
|
.port_ops = &amd33_port_ops
|
|
},
|
|
{ /* 1: Early AMD7409 - no swdma */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x1f, /* UDMA 66 */
|
|
.port_ops = &amd66_port_ops
|
|
},
|
|
{ /* 2: AMD 7409, no swdma errata */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x1f, /* UDMA 66 */
|
|
.port_ops = &amd66_port_ops
|
|
},
|
|
{ /* 3: AMD 7411 */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x3f, /* UDMA 100 */
|
|
.port_ops = &amd100_port_ops
|
|
},
|
|
{ /* 4: AMD 7441 */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x3f, /* UDMA 100 */
|
|
.port_ops = &amd100_port_ops
|
|
},
|
|
{ /* 5: AMD 8111*/
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x7f, /* UDMA 133, no swdma */
|
|
.port_ops = &amd133_port_ops
|
|
},
|
|
{ /* 6: AMD 8111 UDMA 100 (Serenade) */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x3f, /* UDMA 100, no swdma */
|
|
.port_ops = &amd133_port_ops
|
|
},
|
|
{ /* 7: Nvidia Nforce */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x3f, /* UDMA 100 */
|
|
.port_ops = &nv100_port_ops
|
|
},
|
|
{ /* 8: Nvidia Nforce2 and later */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x7f, /* UDMA 133, no swdma */
|
|
.port_ops = &nv133_port_ops
|
|
},
|
|
{ /* 9: AMD CS5536 (Geode companion) */
|
|
.sht = &amd_sht,
|
|
.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f,
|
|
.mwdma_mask = 0x07,
|
|
.udma_mask = 0x3f, /* UDMA 100 */
|
|
.port_ops = &amd100_port_ops
|
|
}
|
|
};
|
|
static struct ata_port_info *port_info[2];
|
|
static int printed_version;
|
|
int type = id->driver_data;
|
|
u8 rev;
|
|
u8 fifo;
|
|
|
|
if (!printed_version++)
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
|
|
|
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
|
pci_read_config_byte(pdev, 0x41, &fifo);
|
|
|
|
/* Check for AMD7409 without swdma errata and if found adjust type */
|
|
if (type == 1 && rev > 0x7)
|
|
type = 2;
|
|
|
|
/* Check for AMD7411 */
|
|
if (type == 3)
|
|
/* FIFO is broken */
|
|
pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
|
|
else
|
|
pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
|
|
|
|
/* Serenade ? */
|
|
if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
|
|
pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
|
|
type = 6; /* UDMA 100 only */
|
|
|
|
if (type < 3)
|
|
ata_pci_clear_simplex(pdev);
|
|
|
|
/* And fire it up */
|
|
|
|
port_info[0] = port_info[1] = &info[type];
|
|
return ata_pci_init_one(pdev, port_info, 2);
|
|
}
|
|
|
|
static const struct pci_device_id amd[] = {
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
|
|
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver amd_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = amd,
|
|
.probe = amd_init_one,
|
|
.remove = ata_pci_remove_one
|
|
};
|
|
|
|
static int __init amd_init(void)
|
|
{
|
|
return pci_register_driver(&amd_pci_driver);
|
|
}
|
|
|
|
static void __exit amd_exit(void)
|
|
{
|
|
pci_unregister_driver(&amd_pci_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, amd);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(amd_init);
|
|
module_exit(amd_exit);
|