72e06d0872
The OMAP powerdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/powerdomain.h to mach-omap2/powerdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access powerdomain code and data directly. As part of this process, remove the references to powerdomain data from the GPIO "driver" and the OMAP PM no-op layer, both in plat-omap. Change the DSPBridge code to point to the new location for the powerdomain headers. The DSPBridge code should not be including the powerdomain headers; these should be removed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com>
243 lines
6.7 KiB
C
243 lines
6.7 KiB
C
/*
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* OMAP2 and OMAP3 powerdomain control
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*
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* Copyright (C) 2009-2010 Texas Instruments, Inc.
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* Copyright (C) 2007-2009 Nokia Corporation
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*
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* Derived from mach-omap2/powerdomain.c written by Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <plat/prcm.h>
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#include "powerdomain.h"
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#include "prm-regbits-34xx.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-34xx.h"
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/* Common functions across OMAP2 and OMAP3 */
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static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL,
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OMAP_POWERSTATE_MASK);
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}
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static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTST,
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OMAP_POWERSTATEST_MASK);
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}
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static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
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m);
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}
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static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL, m);
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}
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static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
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{
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u32 v;
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v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
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omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
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pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
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{
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u32 c = 0;
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/*
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* REVISIT: pwrdm_wait_transition() may be better implemented
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* via a callback and a periodic timer check -- how long do we expect
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* powerdomain transitions to take?
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*/
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/* XXX Is this udelay() value meaningful? */
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while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
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OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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printk(KERN_ERR "powerdomain: waited too long for "
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"powerdomain %s to complete transition\n", pwrdm->name);
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return -EAGAIN;
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}
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pr_debug("powerdomain: completed transition in %d loops\n", c);
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return 0;
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}
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/* Applicable only for OMAP3. Not supported on OMAP2 */
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static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST,
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OMAP3430_LASTPOWERSTATEENTERED_MASK);
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}
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static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTST,
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OMAP3430_LOGICSTATEST_MASK);
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}
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static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL,
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OMAP3430_LOGICSTATEST_MASK);
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}
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static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST,
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OMAP3430_LASTLOGICSTATEENTERED_MASK);
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}
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static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
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{
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switch (bank) {
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case 0:
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return OMAP3430_LASTMEM1STATEENTERED_MASK;
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case 1:
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return OMAP3430_LASTMEM2STATEENTERED_MASK;
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case 2:
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return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
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case 3:
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return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
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default:
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WARN_ON(1); /* should never happen */
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return -EEXIST;
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}
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return 0;
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}
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static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap3_get_mem_bank_lastmemst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST, m);
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}
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static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
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{
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omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
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return 0;
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}
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static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
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{
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return omap2_prm_rmw_mod_reg_bits(0,
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1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
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pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
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}
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static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
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{
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return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
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0, pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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}
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struct pwrdm_ops omap2_pwrdm_operations = {
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.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
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.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
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.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
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.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
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.pwrdm_wait_transition = omap2_pwrdm_wait_transition,
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};
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struct pwrdm_ops omap3_pwrdm_operations = {
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.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
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.pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
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.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
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.pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
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.pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
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.pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
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.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
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.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
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.pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
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.pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
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.pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
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.pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
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.pwrdm_wait_transition = omap2_pwrdm_wait_transition,
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};
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