ec87c99de4
Currently, the macro HAVE_PERF_REGS_SUPPORT is used as a switch to turn on or turn off the code of perf registers. If any architecture cannot support perf register, it disables the perf register parsing, for both the native parsing and cross parsing for other architectures. To support both the native parsing and cross parsing, the tool should always build the perf regs functions. Thus, this patch removes HAVE_PERF_REGS_SUPPORT from the perf regs files. Signed-off-by: Leo Yan <leo.yan@linux.dev> Reviewed-by: Ian Rogers <irogers@google.com> Cc: James Clark <james.clark@arm.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Guo Ren <guoren@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Ming Wang <wangming01@loongson.cn> Cc: John Garry <john.g.garry@oracle.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: linux-csky@vger.kernel.org Cc: linux-riscv@lists.infradead.org Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240214113947.240957-3-leo.yan@linux.dev
89 lines
1.6 KiB
C
89 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include "../perf_regs.h"
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#include "../../../arch/riscv/include/uapi/asm/perf_regs.h"
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const char *__perf_reg_name_riscv(int id)
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{
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switch (id) {
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case PERF_REG_RISCV_PC:
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return "pc";
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case PERF_REG_RISCV_RA:
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return "ra";
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case PERF_REG_RISCV_SP:
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return "sp";
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case PERF_REG_RISCV_GP:
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return "gp";
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case PERF_REG_RISCV_TP:
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return "tp";
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case PERF_REG_RISCV_T0:
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return "t0";
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case PERF_REG_RISCV_T1:
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return "t1";
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case PERF_REG_RISCV_T2:
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return "t2";
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case PERF_REG_RISCV_S0:
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return "s0";
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case PERF_REG_RISCV_S1:
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return "s1";
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case PERF_REG_RISCV_A0:
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return "a0";
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case PERF_REG_RISCV_A1:
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return "a1";
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case PERF_REG_RISCV_A2:
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return "a2";
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case PERF_REG_RISCV_A3:
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return "a3";
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case PERF_REG_RISCV_A4:
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return "a4";
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case PERF_REG_RISCV_A5:
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return "a5";
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case PERF_REG_RISCV_A6:
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return "a6";
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case PERF_REG_RISCV_A7:
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return "a7";
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case PERF_REG_RISCV_S2:
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return "s2";
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case PERF_REG_RISCV_S3:
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return "s3";
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case PERF_REG_RISCV_S4:
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return "s4";
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case PERF_REG_RISCV_S5:
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return "s5";
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case PERF_REG_RISCV_S6:
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return "s6";
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case PERF_REG_RISCV_S7:
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return "s7";
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case PERF_REG_RISCV_S8:
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return "s8";
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case PERF_REG_RISCV_S9:
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return "s9";
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case PERF_REG_RISCV_S10:
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return "s10";
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case PERF_REG_RISCV_S11:
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return "s11";
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case PERF_REG_RISCV_T3:
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return "t3";
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case PERF_REG_RISCV_T4:
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return "t4";
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case PERF_REG_RISCV_T5:
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return "t5";
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case PERF_REG_RISCV_T6:
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return "t6";
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default:
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return NULL;
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}
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return NULL;
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}
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uint64_t __perf_reg_ip_riscv(void)
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{
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return PERF_REG_RISCV_PC;
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}
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uint64_t __perf_reg_sp_riscv(void)
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{
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return PERF_REG_RISCV_SP;
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}
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