ce816e0bac
Add support for R-Car V4M (R8A779H0) SoC power areas to the R-Car SYSC driver. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/eed6faa02c628d32676ab8ea0eee636b4ffd6c47.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
55 lines
2.3 KiB
C
55 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car V4M System Controller
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*
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* Copyright (C) 2023 Renesas Electronics Corp
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*/
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#include <linux/kernel.h>
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#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
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#include "rcar-gen4-sysc.h"
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static struct rcar_gen4_sysc_area r8a779h0_areas[] __initdata = {
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{ "always-on", R8A779H0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "c4", R8A779H0_PD_C4, R8A779H0_PD_ALWAYS_ON },
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{ "a2e0d0", R8A779H0_PD_A2E0D0, R8A779H0_PD_C4, PD_SCU },
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{ "a1e0d0c0", R8A779H0_PD_A1E0D0C0, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c1", R8A779H0_PD_A1E0D0C1, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c2", R8A779H0_PD_A1E0D0C2, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c3", R8A779H0_PD_A1E0D0C3, R8A779H0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a3cr0", R8A779H0_PD_A3CR0, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
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{ "a3cr1", R8A779H0_PD_A3CR1, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
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{ "a3cr2", R8A779H0_PD_A3CR2, R8A779H0_PD_ALWAYS_ON, PD_CPU_NOCR },
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{ "a33dga", R8A779H0_PD_A33DGA, R8A779H0_PD_C4 },
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{ "a23dgb", R8A779H0_PD_A23DGB, R8A779H0_PD_A33DGA },
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{ "a3vip0", R8A779H0_PD_A3VIP0, R8A779H0_PD_C4 },
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{ "a3vip2", R8A779H0_PD_A3VIP2, R8A779H0_PD_C4 },
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{ "a3dul", R8A779H0_PD_A3DUL, R8A779H0_PD_C4 },
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{ "a3isp0", R8A779H0_PD_A3ISP0, R8A779H0_PD_C4 },
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{ "a2cn0", R8A779H0_PD_A2CN0, R8A779H0_PD_C4 },
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{ "a1cn0", R8A779H0_PD_A1CN0, R8A779H0_PD_A2CN0 },
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{ "a1dsp0", R8A779H0_PD_A1DSP0, R8A779H0_PD_A2CN0 },
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{ "a1dsp1", R8A779H0_PD_A1DSP1, R8A779H0_PD_A2CN0 },
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{ "a2imp01", R8A779H0_PD_A2IMP01, R8A779H0_PD_C4 },
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{ "a2psc", R8A779H0_PD_A2PSC, R8A779H0_PD_C4 },
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{ "a2dma", R8A779H0_PD_A2DMA, R8A779H0_PD_C4 },
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{ "a2cv0", R8A779H0_PD_A2CV0, R8A779H0_PD_C4 },
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{ "a2cv1", R8A779H0_PD_A2CV1, R8A779H0_PD_C4 },
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{ "a2cv2", R8A779H0_PD_A2CV2, R8A779H0_PD_C4 },
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{ "a2cv3", R8A779H0_PD_A2CV3, R8A779H0_PD_C4 },
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{ "a3imr0", R8A779H0_PD_A3IMR0, R8A779H0_PD_C4 },
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{ "a3imr1", R8A779H0_PD_A3IMR1, R8A779H0_PD_C4 },
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{ "a3imr2", R8A779H0_PD_A3IMR2, R8A779H0_PD_C4 },
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{ "a3imr3", R8A779H0_PD_A3IMR3, R8A779H0_PD_C4 },
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{ "a3vc", R8A779H0_PD_A3VC, R8A779H0_PD_C4 },
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{ "a3pci", R8A779H0_PD_A3PCI, R8A779H0_PD_C4 },
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{ "a2pciphy", R8A779H0_PD_A2PCIPHY, R8A779H0_PD_A3PCI },
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};
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const struct rcar_gen4_sysc_info r8a779h0_sysc_info __initconst = {
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.areas = r8a779h0_areas,
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.num_areas = ARRAY_SIZE(r8a779h0_areas),
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};
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