08ca6906a4
'nd_pmu->pmu.attr_groups' is dereferenced in function
'nvdimm_pmu_free_hotplug_memory' call after it has been freed. Because in
function 'nvdimm_pmu_free_hotplug_memory' memory pointed by the fields of
'nd_pmu->pmu.attr_groups' is deallocated it is necessary to call 'kfree'
after 'nvdimm_pmu_free_hotplug_memory'.
Fixes: 0fab1ba6ad
("drivers/nvdimm: Add perf interface to expose nvdimm performance stats")
Co-developed-by: Ivanov Mikhail <ivanov.mikhail1@huawei-partners.com>
Signed-off-by: Konstantin Meskhidze <konstantin.meskhidze@huawei.com>
Reviewed-by: Jeff Moyer <jmoyer@redhat.com>
Link: https://lore.kernel.org/r/20230817114103.754977-1-konstantin.meskhidze@huawei.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
331 lines
8.9 KiB
C
331 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* nd_perf.c: NVDIMM Device Performance Monitoring Unit support
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*
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* Perf interface to expose nvdimm performance stats.
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*
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* Copyright (C) 2021 IBM Corporation
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*/
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#define pr_fmt(fmt) "nvdimm_pmu: " fmt
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#include <linux/nd.h>
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#include <linux/platform_device.h>
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#define EVENT(_name, _code) enum{_name = _code}
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/*
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* NVDIMM Events codes.
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*/
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/* Controller Reset Count */
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EVENT(CTL_RES_CNT, 0x1);
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/* Controller Reset Elapsed Time */
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EVENT(CTL_RES_TM, 0x2);
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/* Power-on Seconds */
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EVENT(POWERON_SECS, 0x3);
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/* Life Remaining */
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EVENT(MEM_LIFE, 0x4);
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/* Critical Resource Utilization */
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EVENT(CRI_RES_UTIL, 0x5);
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/* Host Load Count */
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EVENT(HOST_L_CNT, 0x6);
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/* Host Store Count */
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EVENT(HOST_S_CNT, 0x7);
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/* Host Store Duration */
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EVENT(HOST_S_DUR, 0x8);
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/* Host Load Duration */
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EVENT(HOST_L_DUR, 0x9);
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/* Media Read Count */
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EVENT(MED_R_CNT, 0xa);
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/* Media Write Count */
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EVENT(MED_W_CNT, 0xb);
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/* Media Read Duration */
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EVENT(MED_R_DUR, 0xc);
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/* Media Write Duration */
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EVENT(MED_W_DUR, 0xd);
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/* Cache Read Hit Count */
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EVENT(CACHE_RH_CNT, 0xe);
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/* Cache Write Hit Count */
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EVENT(CACHE_WH_CNT, 0xf);
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/* Fast Write Count */
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EVENT(FAST_W_CNT, 0x10);
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NVDIMM_EVENT_ATTR(ctl_res_cnt, CTL_RES_CNT);
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NVDIMM_EVENT_ATTR(ctl_res_tm, CTL_RES_TM);
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NVDIMM_EVENT_ATTR(poweron_secs, POWERON_SECS);
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NVDIMM_EVENT_ATTR(mem_life, MEM_LIFE);
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NVDIMM_EVENT_ATTR(cri_res_util, CRI_RES_UTIL);
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NVDIMM_EVENT_ATTR(host_l_cnt, HOST_L_CNT);
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NVDIMM_EVENT_ATTR(host_s_cnt, HOST_S_CNT);
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NVDIMM_EVENT_ATTR(host_s_dur, HOST_S_DUR);
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NVDIMM_EVENT_ATTR(host_l_dur, HOST_L_DUR);
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NVDIMM_EVENT_ATTR(med_r_cnt, MED_R_CNT);
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NVDIMM_EVENT_ATTR(med_w_cnt, MED_W_CNT);
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NVDIMM_EVENT_ATTR(med_r_dur, MED_R_DUR);
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NVDIMM_EVENT_ATTR(med_w_dur, MED_W_DUR);
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NVDIMM_EVENT_ATTR(cache_rh_cnt, CACHE_RH_CNT);
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NVDIMM_EVENT_ATTR(cache_wh_cnt, CACHE_WH_CNT);
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NVDIMM_EVENT_ATTR(fast_w_cnt, FAST_W_CNT);
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static struct attribute *nvdimm_events_attr[] = {
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NVDIMM_EVENT_PTR(CTL_RES_CNT),
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NVDIMM_EVENT_PTR(CTL_RES_TM),
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NVDIMM_EVENT_PTR(POWERON_SECS),
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NVDIMM_EVENT_PTR(MEM_LIFE),
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NVDIMM_EVENT_PTR(CRI_RES_UTIL),
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NVDIMM_EVENT_PTR(HOST_L_CNT),
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NVDIMM_EVENT_PTR(HOST_S_CNT),
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NVDIMM_EVENT_PTR(HOST_S_DUR),
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NVDIMM_EVENT_PTR(HOST_L_DUR),
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NVDIMM_EVENT_PTR(MED_R_CNT),
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NVDIMM_EVENT_PTR(MED_W_CNT),
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NVDIMM_EVENT_PTR(MED_R_DUR),
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NVDIMM_EVENT_PTR(MED_W_DUR),
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NVDIMM_EVENT_PTR(CACHE_RH_CNT),
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NVDIMM_EVENT_PTR(CACHE_WH_CNT),
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NVDIMM_EVENT_PTR(FAST_W_CNT),
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NULL
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};
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static struct attribute_group nvdimm_pmu_events_group = {
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.name = "events",
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.attrs = nvdimm_events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-4");
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static struct attribute *nvdimm_pmu_format_attr[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group nvdimm_pmu_format_group = {
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.name = "format",
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.attrs = nvdimm_pmu_format_attr,
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};
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ssize_t nvdimm_events_sysfs_show(struct device *dev,
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struct device_attribute *attr, char *page)
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{
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struct perf_pmu_events_attr *pmu_attr;
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pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
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return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
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}
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static ssize_t nvdimm_pmu_cpumask_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pmu *pmu = dev_get_drvdata(dev);
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struct nvdimm_pmu *nd_pmu;
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nd_pmu = container_of(pmu, struct nvdimm_pmu, pmu);
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return cpumap_print_to_pagebuf(true, buf, cpumask_of(nd_pmu->cpu));
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}
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static int nvdimm_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
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{
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struct nvdimm_pmu *nd_pmu;
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u32 target;
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int nodeid;
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const struct cpumask *cpumask;
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nd_pmu = hlist_entry_safe(node, struct nvdimm_pmu, node);
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/* Clear it, incase given cpu is set in nd_pmu->arch_cpumask */
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cpumask_test_and_clear_cpu(cpu, &nd_pmu->arch_cpumask);
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/*
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* If given cpu is not same as current designated cpu for
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* counter access, just return.
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*/
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if (cpu != nd_pmu->cpu)
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return 0;
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/* Check for any active cpu in nd_pmu->arch_cpumask */
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target = cpumask_any(&nd_pmu->arch_cpumask);
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/*
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* Incase we don't have any active cpu in nd_pmu->arch_cpumask,
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* check in given cpu's numa node list.
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*/
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if (target >= nr_cpu_ids) {
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nodeid = cpu_to_node(cpu);
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cpumask = cpumask_of_node(nodeid);
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target = cpumask_any_but(cpumask, cpu);
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}
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nd_pmu->cpu = target;
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/* Migrate nvdimm pmu events to the new target cpu if valid */
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if (target >= 0 && target < nr_cpu_ids)
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perf_pmu_migrate_context(&nd_pmu->pmu, cpu, target);
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return 0;
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}
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static int nvdimm_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
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{
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struct nvdimm_pmu *nd_pmu;
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nd_pmu = hlist_entry_safe(node, struct nvdimm_pmu, node);
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if (nd_pmu->cpu >= nr_cpu_ids)
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nd_pmu->cpu = cpu;
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return 0;
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}
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static int create_cpumask_attr_group(struct nvdimm_pmu *nd_pmu)
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{
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struct perf_pmu_events_attr *pmu_events_attr;
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struct attribute **attrs_group;
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struct attribute_group *nvdimm_pmu_cpumask_group;
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pmu_events_attr = kzalloc(sizeof(*pmu_events_attr), GFP_KERNEL);
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if (!pmu_events_attr)
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return -ENOMEM;
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attrs_group = kzalloc(2 * sizeof(struct attribute *), GFP_KERNEL);
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if (!attrs_group) {
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kfree(pmu_events_attr);
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return -ENOMEM;
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}
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/* Allocate memory for cpumask attribute group */
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nvdimm_pmu_cpumask_group = kzalloc(sizeof(*nvdimm_pmu_cpumask_group), GFP_KERNEL);
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if (!nvdimm_pmu_cpumask_group) {
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kfree(pmu_events_attr);
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kfree(attrs_group);
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return -ENOMEM;
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}
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sysfs_attr_init(&pmu_events_attr->attr.attr);
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pmu_events_attr->attr.attr.name = "cpumask";
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pmu_events_attr->attr.attr.mode = 0444;
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pmu_events_attr->attr.show = nvdimm_pmu_cpumask_show;
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attrs_group[0] = &pmu_events_attr->attr.attr;
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attrs_group[1] = NULL;
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nvdimm_pmu_cpumask_group->attrs = attrs_group;
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nd_pmu->pmu.attr_groups[NVDIMM_PMU_CPUMASK_ATTR] = nvdimm_pmu_cpumask_group;
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return 0;
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}
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static int nvdimm_pmu_cpu_hotplug_init(struct nvdimm_pmu *nd_pmu)
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{
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int nodeid, rc;
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const struct cpumask *cpumask;
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/*
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* Incase of cpu hotplug feature, arch specific code
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* can provide required cpumask which can be used
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* to get designatd cpu for counter access.
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* Check for any active cpu in nd_pmu->arch_cpumask.
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*/
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if (!cpumask_empty(&nd_pmu->arch_cpumask)) {
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nd_pmu->cpu = cpumask_any(&nd_pmu->arch_cpumask);
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} else {
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/* pick active cpu from the cpumask of device numa node. */
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nodeid = dev_to_node(nd_pmu->dev);
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cpumask = cpumask_of_node(nodeid);
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nd_pmu->cpu = cpumask_any(cpumask);
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}
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rc = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "perf/nvdimm:online",
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nvdimm_pmu_cpu_online, nvdimm_pmu_cpu_offline);
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if (rc < 0)
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return rc;
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nd_pmu->cpuhp_state = rc;
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/* Register the pmu instance for cpu hotplug */
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rc = cpuhp_state_add_instance_nocalls(nd_pmu->cpuhp_state, &nd_pmu->node);
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if (rc) {
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cpuhp_remove_multi_state(nd_pmu->cpuhp_state);
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return rc;
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}
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/* Create cpumask attribute group */
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rc = create_cpumask_attr_group(nd_pmu);
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if (rc) {
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cpuhp_state_remove_instance_nocalls(nd_pmu->cpuhp_state, &nd_pmu->node);
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cpuhp_remove_multi_state(nd_pmu->cpuhp_state);
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return rc;
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}
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return 0;
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}
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static void nvdimm_pmu_free_hotplug_memory(struct nvdimm_pmu *nd_pmu)
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{
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cpuhp_state_remove_instance_nocalls(nd_pmu->cpuhp_state, &nd_pmu->node);
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cpuhp_remove_multi_state(nd_pmu->cpuhp_state);
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if (nd_pmu->pmu.attr_groups[NVDIMM_PMU_CPUMASK_ATTR])
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kfree(nd_pmu->pmu.attr_groups[NVDIMM_PMU_CPUMASK_ATTR]->attrs);
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kfree(nd_pmu->pmu.attr_groups[NVDIMM_PMU_CPUMASK_ATTR]);
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}
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int register_nvdimm_pmu(struct nvdimm_pmu *nd_pmu, struct platform_device *pdev)
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{
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int rc;
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if (!nd_pmu || !pdev)
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return -EINVAL;
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/* event functions like add/del/read/event_init and pmu name should not be NULL */
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if (WARN_ON_ONCE(!(nd_pmu->pmu.event_init && nd_pmu->pmu.add &&
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nd_pmu->pmu.del && nd_pmu->pmu.read && nd_pmu->pmu.name)))
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return -EINVAL;
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nd_pmu->pmu.attr_groups = kzalloc((NVDIMM_PMU_NULL_ATTR + 1) *
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sizeof(struct attribute_group *), GFP_KERNEL);
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if (!nd_pmu->pmu.attr_groups)
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return -ENOMEM;
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/*
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* Add platform_device->dev pointer to nvdimm_pmu to access
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* device data in events functions.
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*/
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nd_pmu->dev = &pdev->dev;
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/* Fill attribute groups for the nvdimm pmu device */
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nd_pmu->pmu.attr_groups[NVDIMM_PMU_FORMAT_ATTR] = &nvdimm_pmu_format_group;
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nd_pmu->pmu.attr_groups[NVDIMM_PMU_EVENT_ATTR] = &nvdimm_pmu_events_group;
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nd_pmu->pmu.attr_groups[NVDIMM_PMU_NULL_ATTR] = NULL;
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/* Fill attribute group for cpumask */
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rc = nvdimm_pmu_cpu_hotplug_init(nd_pmu);
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if (rc) {
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pr_info("cpu hotplug feature failed for device: %s\n", nd_pmu->pmu.name);
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kfree(nd_pmu->pmu.attr_groups);
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return rc;
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}
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rc = perf_pmu_register(&nd_pmu->pmu, nd_pmu->pmu.name, -1);
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if (rc) {
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nvdimm_pmu_free_hotplug_memory(nd_pmu);
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kfree(nd_pmu->pmu.attr_groups);
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return rc;
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}
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pr_info("%s NVDIMM performance monitor support registered\n",
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nd_pmu->pmu.name);
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return 0;
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}
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EXPORT_SYMBOL_GPL(register_nvdimm_pmu);
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void unregister_nvdimm_pmu(struct nvdimm_pmu *nd_pmu)
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{
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perf_pmu_unregister(&nd_pmu->pmu);
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nvdimm_pmu_free_hotplug_memory(nd_pmu);
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kfree(nd_pmu->pmu.attr_groups);
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kfree(nd_pmu);
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}
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EXPORT_SYMBOL_GPL(unregister_nvdimm_pmu);
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