de49ea38ba
Introduce the mechanism to lock/unlock the device 'deep sleep' mode. When the PCIe link state is L1.2 or L2, the host side still can keep the device is in D0 state from the host side point of view. At the same time, if the device's 'deep sleep' mode is unlocked, the device will go to 'deep sleep' while it is still in D0 state on the host side. Signed-off-by: Haijun Liu <haijun.liu@mediatek.com> Signed-off-by: Chandrashekar Devegowda <chandrashekar.devegowda@intel.com> Co-developed-by: Ricardo Martinez <ricardo.martinez@linux.intel.com> Signed-off-by: Ricardo Martinez <ricardo.martinez@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/completion.h>
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#include <linux/dev_printk.h>
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#include <linux/io.h>
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#include <linux/irqreturn.h>
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#include "t7xx_mhccif.h"
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#include "t7xx_modem_ops.h"
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#include "t7xx_pci.h"
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#include "t7xx_pcie_mac.h"
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#include "t7xx_reg.h"
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#define D2H_INT_SR_ACK (D2H_INT_SUSPEND_ACK | \
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D2H_INT_RESUME_ACK | \
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D2H_INT_SUSPEND_ACK_AP | \
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D2H_INT_RESUME_ACK_AP)
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static void t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev *t7xx_dev, u32 mask)
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{
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void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
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/* Clear level 2 interrupt */
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iowrite32(mask, mhccif_pbase + REG_EP2RC_SW_INT_ACK);
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/* Ensure write is complete */
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t7xx_mhccif_read_sw_int_sts(t7xx_dev);
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/* Clear level 1 interrupt */
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t7xx_pcie_mac_clear_int_status(t7xx_dev, MHCCIF_INT);
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}
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static irqreturn_t t7xx_mhccif_isr_thread(int irq, void *data)
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{
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struct t7xx_pci_dev *t7xx_dev = data;
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u32 int_status, val;
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val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
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iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);
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int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
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if (int_status & D2H_SW_INT_MASK) {
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int ret = t7xx_pci_mhccif_isr(t7xx_dev);
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if (ret)
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dev_err(&t7xx_dev->pdev->dev, "PCI MHCCIF ISR failure: %d", ret);
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}
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t7xx_mhccif_clear_interrupts(t7xx_dev, int_status);
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if (int_status & D2H_INT_DS_LOCK_ACK)
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complete_all(&t7xx_dev->sleep_lock_acquire);
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if (int_status & D2H_INT_SR_ACK)
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complete(&t7xx_dev->pm_sr_ack);
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iowrite32(T7XX_L1_BIT(1), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);
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int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
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if (!int_status) {
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val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
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iowrite32(val, IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR);
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}
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t7xx_pcie_mac_set_int(t7xx_dev, MHCCIF_INT);
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return IRQ_HANDLED;
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}
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u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev)
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{
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return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS);
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}
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void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val)
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{
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iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET);
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}
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void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val)
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{
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iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR);
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}
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u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev)
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{
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return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK);
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}
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static irqreturn_t t7xx_mhccif_isr_handler(int irq, void *data)
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{
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return IRQ_WAKE_THREAD;
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}
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void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev)
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{
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t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base +
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MHCCIF_RC_DEV_BASE -
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t7xx_dev->base_addr.pcie_dev_reg_trsl_addr;
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t7xx_dev->intr_handler[MHCCIF_INT] = t7xx_mhccif_isr_handler;
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t7xx_dev->intr_thread[MHCCIF_INT] = t7xx_mhccif_isr_thread;
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t7xx_dev->callback_param[MHCCIF_INT] = t7xx_dev;
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}
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void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel)
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{
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void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
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iowrite32(BIT(channel), mhccif_pbase + REG_RC2EP_SW_BSY);
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iowrite32(channel, mhccif_pbase + REG_RC2EP_SW_TCHNUM);
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}
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