b12deb5e86
According to the firmware behavior (even the oldest one in linux-firmware)
If the firmware is downloaded, MT7921S must rely on the additional mailbox
mechanism that resides in firmware to check if the device is the right
state for mt7921s_mcu_[fw|drv]_pmctrl. Otherwise, we still apply the old
way for that.
That is a necessary patch before we enable runtime pm for mt7921s as
default.
Fixes: 48fab5bbef ("mt76: mt7921: introduce mt7921s support")
Co-developed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Leon Yen <leon.yen@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
141 lines
4.0 KiB
C
141 lines
4.0 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*/
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#ifndef __MT76S_H
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#define __MT76S_H
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#define MT_PSE_PAGE_SZ 128
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#define MCR_WCIR 0x0000
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#define MCR_WHLPCR 0x0004
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#define WHLPCR_FW_OWN_REQ_CLR BIT(9)
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#define WHLPCR_FW_OWN_REQ_SET BIT(8)
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#define WHLPCR_IS_DRIVER_OWN BIT(8)
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#define WHLPCR_INT_EN_CLR BIT(1)
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#define WHLPCR_INT_EN_SET BIT(0)
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#define MCR_WSDIOCSR 0x0008
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#define MCR_WHCR 0x000C
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#define W_INT_CLR_CTRL BIT(1)
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#define RECV_MAILBOX_RD_CLR_EN BIT(2)
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#define WF_SYS_RSTB BIT(4) /* supported in CONNAC2 */
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#define WF_WHOLE_PATH_RSTB BIT(5) /* supported in CONNAC2 */
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#define WF_SDIO_WF_PATH_RSTB BIT(6) /* supported in CONNAC2 */
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#define MAX_HIF_RX_LEN_NUM GENMASK(13, 8)
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#define MAX_HIF_RX_LEN_NUM_CONNAC2 GENMASK(14, 8) /* supported in CONNAC2 */
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#define WF_RST_DONE BIT(15) /* supported in CONNAC2 */
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#define RX_ENHANCE_MODE BIT(16)
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#define MCR_WHISR 0x0010
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#define MCR_WHIER 0x0014
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#define WHIER_D2H_SW_INT GENMASK(31, 8)
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#define WHIER_FW_OWN_BACK_INT_EN BIT(7)
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#define WHIER_ABNORMAL_INT_EN BIT(6)
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#define WHIER_WDT_INT_EN BIT(5) /* supported in CONNAC2 */
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#define WHIER_RX1_DONE_INT_EN BIT(2)
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#define WHIER_RX0_DONE_INT_EN BIT(1)
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#define WHIER_TX_DONE_INT_EN BIT(0)
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#define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
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WHIER_RX1_DONE_INT_EN | \
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WHIER_TX_DONE_INT_EN | \
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WHIER_ABNORMAL_INT_EN | \
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WHIER_D2H_SW_INT)
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#define MCR_WASR 0x0020
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#define MCR_WSICR 0x0024
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#define MCR_WTSR0 0x0028
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#define TQ0_CNT GENMASK(7, 0)
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#define TQ1_CNT GENMASK(15, 8)
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#define TQ2_CNT GENMASK(23, 16)
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#define TQ3_CNT GENMASK(31, 24)
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#define MCR_WTSR1 0x002c
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#define TQ4_CNT GENMASK(7, 0)
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#define TQ5_CNT GENMASK(15, 8)
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#define TQ6_CNT GENMASK(23, 16)
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#define TQ7_CNT GENMASK(31, 24)
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#define MCR_WTDR1 0x0034
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#define MCR_WRDR0 0x0050
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#define MCR_WRDR1 0x0054
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#define MCR_WRDR(p) (0x0050 + 4 * (p))
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#define MCR_H2DSM0R 0x0070
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#define H2D_SW_INT_READ BIT(16)
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#define H2D_SW_INT_WRITE BIT(17)
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#define H2D_SW_INT_CLEAR_MAILBOX_ACK BIT(22)
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#define MCR_H2DSM1R 0x0074
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#define MCR_D2HRM0R 0x0078
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#define MCR_D2HRM1R 0x007c
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#define MCR_D2HRM2R 0x0080
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#define MCR_WRPLR 0x0090
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#define RX0_PACKET_LENGTH GENMASK(15, 0)
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#define RX1_PACKET_LENGTH GENMASK(31, 16)
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#define MCR_WTMDR 0x00b0
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#define MCR_WTMCR 0x00b4
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#define MCR_WTMDPCR0 0x00b8
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#define MCR_WTMDPCR1 0x00bc
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#define MCR_WPLRCR 0x00d4
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#define MCR_WSR 0x00D8
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#define MCR_CLKIOCR 0x0100
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#define MCR_CMDIOCR 0x0104
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#define MCR_DAT0IOCR 0x0108
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#define MCR_DAT1IOCR 0x010C
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#define MCR_DAT2IOCR 0x0110
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#define MCR_DAT3IOCR 0x0114
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#define MCR_CLKDLYCR 0x0118
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#define MCR_CMDDLYCR 0x011C
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#define MCR_ODATDLYCR 0x0120
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#define MCR_IDATDLYCR1 0x0124
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#define MCR_IDATDLYCR2 0x0128
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#define MCR_ILCHCR 0x012C
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#define MCR_WTQCR0 0x0130
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#define MCR_WTQCR1 0x0134
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#define MCR_WTQCR2 0x0138
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#define MCR_WTQCR3 0x013C
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#define MCR_WTQCR4 0x0140
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#define MCR_WTQCR5 0x0144
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#define MCR_WTQCR6 0x0148
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#define MCR_WTQCR7 0x014C
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#define MCR_WTQCR(x) (0x130 + 4 * (x))
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#define TXQ_CNT_L GENMASK(15, 0)
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#define TXQ_CNT_H GENMASK(31, 16)
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#define MCR_SWPCDBGR 0x0154
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#define MCR_H2DSM2R 0x0160 /* supported in CONNAC2 */
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#define MCR_H2DSM3R 0x0164 /* supported in CONNAC2 */
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#define MCR_D2HRM3R 0x0174 /* supported in CONNAC2 */
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#define D2HRM3R_IS_DRIVER_OWN BIT(0)
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#define MCR_WTQCR8 0x0190 /* supported in CONNAC2 */
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#define MCR_WTQCR9 0x0194 /* supported in CONNAC2 */
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#define MCR_WTQCR10 0x0198 /* supported in CONNAC2 */
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#define MCR_WTQCR11 0x019C /* supported in CONNAC2 */
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#define MCR_WTQCR12 0x01A0 /* supported in CONNAC2 */
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#define MCR_WTQCR13 0x01A4 /* supported in CONNAC2 */
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#define MCR_WTQCR14 0x01A8 /* supported in CONNAC2 */
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#define MCR_WTQCR15 0x01AC /* supported in CONNAC2 */
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enum mt76_connac_sdio_ver {
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MT76_CONNAC_SDIO,
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MT76_CONNAC2_SDIO,
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};
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struct mt76s_intr {
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u32 isr;
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u32 *rec_mb;
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struct {
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u32 *wtqcr;
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} tx;
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struct {
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u16 *len[2];
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u16 *num;
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} rx;
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};
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#endif
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