f60e5fb6df
All of the config data files and all of the register definition files (plus a few others) use GSI_EE_AP, which is defined in "ipa_version.h". Include that header where it's needed. All of the IPA register definition files include "../ipa.h", though none of them need anything defined there. Similarly, all of the GSI register definition files include "../gsi.h", but don't need anything defined there. Remove these unnneded includes. All of the configuration data files include "../gsi.h", though none of them need anything defined there, so remove these includes. Remove other includes of local header files that are not required. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
316 lines
9.9 KiB
C
316 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2023-2024 Linaro Ltd. */
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#include <linux/array_size.h>
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#include <linux/bits.h>
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#include <linux/types.h>
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#include "../gsi_reg.h"
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#include "../ipa_version.h"
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#include "../reg.h"
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REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
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0x0000c020 + 0x1000 * GSI_EE_AP);
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REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
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0x0000c024 + 0x1000 * GSI_EE_AP);
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static const u32 reg_ch_c_cntxt_0_fmask[] = {
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[CHTYPE_PROTOCOL] = GENMASK(2, 0),
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[CHTYPE_DIR] = BIT(3),
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[CH_EE] = GENMASK(7, 4),
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[CHID] = GENMASK(12, 8),
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[CHTYPE_PROTOCOL_MSB] = BIT(13),
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[ERINDEX] = GENMASK(18, 14),
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/* Bit 19 reserved */
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[CHSTATE] = GENMASK(23, 20),
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[ELEMENT_SIZE] = GENMASK(31, 24),
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};
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REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
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0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_ch_c_cntxt_1_fmask[] = {
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[CH_R_LENGTH] = GENMASK(19, 0),
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/* Bits 20-31 reserved */
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};
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REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
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0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_ch_c_qos_fmask[] = {
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[WRR_WEIGHT] = GENMASK(3, 0),
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/* Bits 4-7 reserved */
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[MAX_PREFETCH] = BIT(8),
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[USE_DB_ENG] = BIT(9),
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[PREFETCH_MODE] = GENMASK(13, 10),
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/* Bits 14-15 reserved */
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[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
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[DB_IN_BYTES] = BIT(24),
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/* Bits 25-31 reserved */
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};
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REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_error_log_fmask[] = {
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[ERR_ARG3] = GENMASK(3, 0),
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[ERR_ARG2] = GENMASK(7, 4),
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[ERR_ARG1] = GENMASK(11, 8),
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[ERR_CODE] = GENMASK(15, 12),
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/* Bits 16-18 reserved */
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[ERR_VIRT_IDX] = GENMASK(23, 19),
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[ERR_TYPE] = GENMASK(27, 24),
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[ERR_EE] = GENMASK(31, 28),
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};
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REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
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0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
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0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
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0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
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0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
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[EV_CHTYPE] = GENMASK(3, 0),
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[EV_EE] = GENMASK(7, 4),
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[EV_EVCHID] = GENMASK(15, 8),
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[EV_INTYPE] = BIT(16),
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/* Bits 17-19 reserved */
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[EV_CHSTATE] = GENMASK(23, 20),
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[EV_ELEMENT_SIZE] = GENMASK(31, 24),
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};
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REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
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0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
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[R_LENGTH] = GENMASK(19, 0),
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};
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REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
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0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
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0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
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0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
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0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
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static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
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[EV_MODT] = GENMASK(15, 0),
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[EV_MODC] = GENMASK(23, 16),
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[EV_MOD_CNT] = GENMASK(31, 24),
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};
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REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
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0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
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0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
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0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
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0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
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0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
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0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
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0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
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0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
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REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
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0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
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REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
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0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
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static const u32 reg_gsi_status_fmask[] = {
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[ENABLED] = BIT(0),
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/* Bits 1-31 reserved */
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};
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REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
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static const u32 reg_ch_cmd_fmask[] = {
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[CH_CHID] = GENMASK(7, 0),
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/* Bits 8-23 reserved */
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[CH_OPCODE] = GENMASK(31, 24),
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};
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REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
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static const u32 reg_ev_ch_cmd_fmask[] = {
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[EV_CHID] = GENMASK(7, 0),
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/* Bits 8-23 reserved */
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[EV_OPCODE] = GENMASK(31, 24),
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};
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REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
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static const u32 reg_generic_cmd_fmask[] = {
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[GENERIC_OPCODE] = GENMASK(4, 0),
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[GENERIC_CHID] = GENMASK(9, 5),
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[GENERIC_EE] = GENMASK(13, 10),
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/* Bits 14-23 reserved */
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[GENERIC_PARAMS] = GENMASK(31, 24),
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};
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REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
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static const u32 reg_hw_param_2_fmask[] = {
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[IRAM_SIZE] = GENMASK(2, 0),
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[NUM_CH_PER_EE] = GENMASK(7, 3),
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[NUM_EV_PER_EE] = GENMASK(12, 8),
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[GSI_CH_PEND_TRANSLATE] = BIT(13),
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[GSI_CH_FULL_LOGIC] = BIT(14),
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[GSI_USE_SDMA] = BIT(15),
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[GSI_SDMA_N_INT] = GENMASK(18, 16),
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[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
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[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
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[GSI_USE_RD_WR_ENG] = BIT(30),
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[GSI_USE_INTER_EE] = BIT(31),
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};
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REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
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0x00012098 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
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0x0001209c + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
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0x000120a0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
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0x000120a4 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
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0x000120b8 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
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0x000120c0 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
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REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
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static const u32 reg_cntxt_intset_fmask[] = {
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[INTYPE] = BIT(0)
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/* Bits 1-31 reserved */
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};
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REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
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REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
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REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
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static const u32 reg_cntxt_scratch_0_fmask[] = {
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[INTER_EE_RESULT] = GENMASK(2, 0),
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/* Bits 3-4 reserved */
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[GENERIC_EE_RESULT] = GENMASK(7, 5),
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/* Bits 8-31 reserved */
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};
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REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
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static const struct reg *reg_array[] = {
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[INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
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[INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
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[CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
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[CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
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[CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
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[CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
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[CH_C_QOS] = ®_ch_c_qos,
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[CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
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[CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
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[CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
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[CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
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[EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
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[EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
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[EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
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[EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
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[EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
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[EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
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[EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
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[EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
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[EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
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[EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
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[EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
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[EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
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[EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
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[CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
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[EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
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[GSI_STATUS] = ®_gsi_status,
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[CH_CMD] = ®_ch_cmd,
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[EV_CH_CMD] = ®_ev_ch_cmd,
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[GENERIC_CMD] = ®_generic_cmd,
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[HW_PARAM_2] = ®_hw_param_2,
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[CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
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[CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
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[CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
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[CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
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[CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
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[CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
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[CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
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[CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
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[CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
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[CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
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[CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
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[CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
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[CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
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[CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
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[CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
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[CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
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[CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
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[CNTXT_INTSET] = ®_cntxt_intset,
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[ERROR_LOG] = ®_error_log,
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[ERROR_LOG_CLR] = ®_error_log_clr,
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[CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
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};
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const struct regs gsi_regs_v4_11 = {
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.reg_count = ARRAY_SIZE(reg_array),
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.reg = reg_array,
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};
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