9055a2f591
After the recent ixp4xx cleanups, the ptp driver has gained a
build failure in some configurations:
drivers/net/ethernet/xscale/ptp_ixp46x.c: In function 'ptp_ixp_init':
drivers/net/ethernet/xscale/ptp_ixp46x.c:290:51: error: 'IXP4XX_TIMESYNC_BASE_VIRT' undeclared (first use in this function)
Avoid the last bit of hardcoded constants from platform headers
by turning the ptp driver bit into a platform driver and passing
the IRQ and MMIO address as resources.
This is a bit tricky:
- The interface between the two drivers is now the new
ixp46x_ptp_find() function, replacing the global
ixp46x_phc_index variable. The call is done as late
as possible, in hwtstamp_set(), to ensure that the
ptp device is fully probed.
- As the ptp driver is now called by the network driver, the
link dependency is reversed, which in turn requires a small
Makefile hack
- The GPIO number is still left hardcoded. This is clearly not
great, but it can be addressed later. Note that commit 98ac0cc270
("ARM: ixp4xx: Convert to MULTI_IRQ_HANDLER") changed the
IRQ number to something meaningless. Passing the correct IRQ
in a resource fixes this.
- When the PTP driver is disabled, ethtool .get_ts_info()
now correctly lists only software timestamping regardless
of the hardware.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[Fix a missing include]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PTP 1588 clock using the IXP46X
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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*/
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#ifndef _IXP46X_TS_H_
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#define _IXP46X_TS_H_
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#define DEFAULT_ADDEND 0xF0000029
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#define TICKS_NS_SHIFT 4
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struct ixp46x_channel_ctl {
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u32 ch_control; /* 0x40 Time Synchronization Channel Control */
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u32 ch_event; /* 0x44 Time Synchronization Channel Event */
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u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
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u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
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u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
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u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
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u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
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u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
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};
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struct ixp46x_ts_regs {
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u32 control; /* 0x00 Time Sync Control Register */
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u32 event; /* 0x04 Time Sync Event Register */
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u32 addend; /* 0x08 Time Sync Addend Register */
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u32 accum; /* 0x0C Time Sync Accumulator Register */
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u32 test; /* 0x10 Time Sync Test Register */
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u32 unused; /* 0x14 */
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u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
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u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
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u32 systime_lo; /* 0x20 SystemTime_Low Register */
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u32 systime_hi; /* 0x24 SystemTime_High Register */
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u32 trgt_lo; /* 0x28 TargetTime_Low Register */
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u32 trgt_hi; /* 0x2C TargetTime_High Register */
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u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
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u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
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u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
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u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
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struct ixp46x_channel_ctl channel[3];
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};
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/* 0x00 Time Sync Control Register Bits */
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#define TSCR_AMM (1<<3)
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#define TSCR_ASM (1<<2)
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#define TSCR_TTM (1<<1)
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#define TSCR_RST (1<<0)
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/* 0x04 Time Sync Event Register Bits */
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#define TSER_SNM (1<<3)
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#define TSER_SNS (1<<2)
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#define TTIPEND (1<<1)
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/* 0x40 Time Synchronization Channel Control Register Bits */
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#define MASTER_MODE (1<<0)
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#define TIMESTAMP_ALL (1<<1)
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/* 0x44 Time Synchronization Channel Event Register Bits */
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#define TX_SNAPSHOT_LOCKED (1<<0)
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#define RX_SNAPSHOT_LOCKED (1<<1)
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK_IXP46X)
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int ixp46x_ptp_find(struct ixp46x_ts_regs *__iomem *regs, int *phc_index);
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#else
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static inline int ixp46x_ptp_find(struct ixp46x_ts_regs *__iomem *regs, int *phc_index)
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{
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*regs = NULL;
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*phc_index = -1;
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return -ENODEV;
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}
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#endif
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#endif
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