be5f81d37f
Instead of using hard coded clock increment values for each SoC derive the clock increment from the module clock. This is done in preparation to support a second platform, R-Car V4H that uses a 200Mhz clock compared with the 320Mhz clock used on R-Car S4. Tested on both SoCs, S4 reports a clock of 320000000Hz which gives a value of 0x19000000. Documentation says a 320Mhz clock is used and the correct increment for that clock is 0x19000000. V4H reports a clock of 199999992Hz which gives a value of 0x2800001a. Documentation says a 200Mhz clock is used and the correct increment for that clock is 0x28000000. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Renesas R-Car Gen4 gPTP device driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation
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*/
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#ifndef __RCAR_GEN4_PTP_H__
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#define __RCAR_GEN4_PTP_H__
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#include <linux/ptp_clock_kernel.h>
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#define RCAR_GEN4_GPTP_OFFSET_S4 0x00018000
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enum rcar_gen4_ptp_reg_layout {
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RCAR_GEN4_PTP_REG_LAYOUT
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};
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/* driver's definitions */
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#define RCAR_GEN4_RXTSTAMP_ENABLED BIT(0)
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#define RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT BIT(1)
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#define RCAR_GEN4_RXTSTAMP_TYPE_ALL (RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT | BIT(2))
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#define RCAR_GEN4_RXTSTAMP_TYPE RCAR_GEN4_RXTSTAMP_TYPE_ALL
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#define RCAR_GEN4_TXTSTAMP_ENABLED BIT(0)
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#define PTPRO 0
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enum rcar_gen4_ptp_reg {
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PTPTMEC = PTPRO + 0x0010,
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PTPTMDC = PTPRO + 0x0014,
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PTPTIVC0 = PTPRO + 0x0020,
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PTPTOVC00 = PTPRO + 0x0030,
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PTPTOVC10 = PTPRO + 0x0034,
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PTPTOVC20 = PTPRO + 0x0038,
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PTPGPTPTM00 = PTPRO + 0x0050,
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PTPGPTPTM10 = PTPRO + 0x0054,
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PTPGPTPTM20 = PTPRO + 0x0058,
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};
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struct rcar_gen4_ptp_reg_offset {
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u16 enable;
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u16 disable;
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u16 increment;
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u16 config_t0;
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u16 config_t1;
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u16 config_t2;
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u16 monitor_t0;
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u16 monitor_t1;
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u16 monitor_t2;
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};
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struct rcar_gen4_ptp_private {
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void __iomem *addr;
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struct ptp_clock *clock;
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struct ptp_clock_info info;
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const struct rcar_gen4_ptp_reg_offset *offs;
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spinlock_t lock; /* For multiple registers access */
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u32 tstamp_tx_ctrl;
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u32 tstamp_rx_ctrl;
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s64 default_addend;
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bool initialized;
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};
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int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,
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enum rcar_gen4_ptp_reg_layout layout, u32 rate);
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int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv);
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struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev);
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#endif /* #ifndef __RCAR_GEN4_PTP_H__ */
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