ea97374214
Use linux kernel version for ethtool and module versions. Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Acked-by: Chris Snook <chris.snook@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
493 lines
17 KiB
C
493 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright(c) 2007 Atheros Corporation. All rights reserved.
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* Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*/
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#ifndef _ATL1E_H_
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#define _ATL1E_H_
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/in.h>
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#include <linux/ip.h>
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#include <linux/ipv6.h>
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#include <linux/udp.h>
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#include <linux/mii.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <linux/pagemap.h>
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#include <linux/tcp.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/workqueue.h>
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#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include "atl1e_hw.h"
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#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
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#define CMD_IO_SPACE 0x0001
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#define CMD_MEMORY_SPACE 0x0002
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#define CMD_BUS_MASTER 0x0004
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#define BAR_0 0
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#define BAR_1 1
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#define BAR_5 5
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/* Wake Up Filter Control */
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#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
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#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define SPEED_0 0xffff
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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/* Error Codes */
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#define AT_ERR_EEPROM 1
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#define AT_ERR_PHY 2
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#define AT_ERR_CONFIG 3
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#define AT_ERR_PARAM 4
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#define AT_ERR_MAC_TYPE 5
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#define AT_ERR_PHY_TYPE 6
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#define AT_ERR_PHY_SPEED 7
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#define AT_ERR_PHY_RES 8
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#define AT_ERR_TIMEOUT 9
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#define MAX_JUMBO_FRAME_SIZE 0x2000
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#define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) \
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_tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
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(((_vlan) >> 9) & 8))
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#define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) \
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_vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
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(((_tdp) & 0x88) << 5))
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#define AT_MAX_RECEIVE_QUEUE 4
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#define AT_PAGE_NUM_PER_QUEUE 2
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#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
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#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
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#define AT_TX_WATCHDOG (5 * HZ)
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#define AT_MAX_INT_WORK 10
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#define AT_TWSI_EEPROM_TIMEOUT 100
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#define AT_HW_MAX_IDLE_DELAY 10
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#define AT_SUSPEND_LINK_TIMEOUT 28
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#define AT_REGS_LEN 75
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#define AT_EEPROM_LEN 512
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#define AT_ADV_MASK (ADVERTISE_10_HALF |\
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ADVERTISE_10_FULL |\
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ADVERTISE_100_HALF |\
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ADVERTISE_100_FULL |\
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ADVERTISE_1000_FULL)
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/* tpd word 2 */
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#define TPD_BUFLEN_MASK 0x3FFF
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#define TPD_BUFLEN_SHIFT 0
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#define TPD_DMAINT_MASK 0x0001
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#define TPD_DMAINT_SHIFT 14
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#define TPD_PKTNT_MASK 0x0001
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#define TPD_PKTINT_SHIFT 15
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#define TPD_VLANTAG_MASK 0xFFFF
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#define TPD_VLAN_SHIFT 16
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/* tpd word 3 bits 0:4 */
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#define TPD_EOP_MASK 0x0001
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#define TPD_EOP_SHIFT 0
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#define TPD_IP_VERSION_MASK 0x0001
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#define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */
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#define TPD_INS_VL_TAG_MASK 0x0001
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#define TPD_INS_VL_TAG_SHIFT 2
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#define TPD_CC_SEGMENT_EN_MASK 0x0001
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#define TPD_CC_SEGMENT_EN_SHIFT 3
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#define TPD_SEGMENT_EN_MASK 0x0001
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#define TPD_SEGMENT_EN_SHIFT 4
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/* tdp word 3 bits 5:7 if ip version is 0 */
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#define TPD_IP_CSUM_MASK 0x0001
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#define TPD_IP_CSUM_SHIFT 5
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#define TPD_TCP_CSUM_MASK 0x0001
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#define TPD_TCP_CSUM_SHIFT 6
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#define TPD_UDP_CSUM_MASK 0x0001
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#define TPD_UDP_CSUM_SHIFT 7
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/* tdp word 3 bits 5:7 if ip version is 1 */
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#define TPD_V6_IPHLLO_MASK 0x0007
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#define TPD_V6_IPHLLO_SHIFT 7
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/* tpd word 3 bits 8:9 bit */
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#define TPD_VL_TAGGED_MASK 0x0001
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#define TPD_VL_TAGGED_SHIFT 8
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#define TPD_ETHTYPE_MASK 0x0001
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#define TPD_ETHTYPE_SHIFT 9
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/* tdp word 3 bits 10:13 if ip version is 0 */
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#define TDP_V4_IPHL_MASK 0x000F
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#define TPD_V4_IPHL_SHIFT 10
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/* tdp word 3 bits 10:13 if ip version is 1 */
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#define TPD_V6_IPHLHI_MASK 0x000F
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#define TPD_V6_IPHLHI_SHIFT 10
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/* tpd word 3 bit 14:31 if segment enabled */
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#define TPD_TCPHDRLEN_MASK 0x000F
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#define TPD_TCPHDRLEN_SHIFT 14
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#define TPD_HDRFLAG_MASK 0x0001
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#define TPD_HDRFLAG_SHIFT 18
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#define TPD_MSS_MASK 0x1FFF
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#define TPD_MSS_SHIFT 19
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/* tdp word 3 bit 16:31 if custom csum enabled */
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#define TPD_PLOADOFFSET_MASK 0x00FF
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#define TPD_PLOADOFFSET_SHIFT 16
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#define TPD_CCSUMOFFSET_MASK 0x00FF
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#define TPD_CCSUMOFFSET_SHIFT 24
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struct atl1e_tpd_desc {
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__le64 buffer_addr;
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__le32 word2;
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__le32 word3;
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};
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/* how about 0x2000 */
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#define MAX_TX_BUF_LEN 0x2000
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#define MAX_TX_BUF_SHIFT 13
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#define MAX_TSO_SEG_SIZE 0x3c00
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/* rrs word 1 bit 0:31 */
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#define RRS_RX_CSUM_MASK 0xFFFF
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#define RRS_RX_CSUM_SHIFT 0
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#define RRS_PKT_SIZE_MASK 0x3FFF
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#define RRS_PKT_SIZE_SHIFT 16
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#define RRS_CPU_NUM_MASK 0x0003
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#define RRS_CPU_NUM_SHIFT 30
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#define RRS_IS_RSS_IPV4 0x0001
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#define RRS_IS_RSS_IPV4_TCP 0x0002
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#define RRS_IS_RSS_IPV6 0x0004
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#define RRS_IS_RSS_IPV6_TCP 0x0008
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#define RRS_IS_IPV6 0x0010
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#define RRS_IS_IP_FRAG 0x0020
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#define RRS_IS_IP_DF 0x0040
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#define RRS_IS_802_3 0x0080
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#define RRS_IS_VLAN_TAG 0x0100
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#define RRS_IS_ERR_FRAME 0x0200
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#define RRS_IS_IPV4 0x0400
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#define RRS_IS_UDP 0x0800
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#define RRS_IS_TCP 0x1000
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#define RRS_IS_BCAST 0x2000
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#define RRS_IS_MCAST 0x4000
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#define RRS_IS_PAUSE 0x8000
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#define RRS_ERR_BAD_CRC 0x0001
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#define RRS_ERR_CODE 0x0002
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#define RRS_ERR_DRIBBLE 0x0004
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#define RRS_ERR_RUNT 0x0008
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#define RRS_ERR_RX_OVERFLOW 0x0010
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#define RRS_ERR_TRUNC 0x0020
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#define RRS_ERR_IP_CSUM 0x0040
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#define RRS_ERR_L4_CSUM 0x0080
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#define RRS_ERR_LENGTH 0x0100
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#define RRS_ERR_DES_ADDR 0x0200
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struct atl1e_recv_ret_status {
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u16 seq_num;
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u16 hash_lo;
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__le32 word1;
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u16 pkt_flag;
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u16 err_flag;
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u16 hash_hi;
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u16 vtag;
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};
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enum atl1e_dma_req_block {
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atl1e_dma_req_128 = 0,
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atl1e_dma_req_256 = 1,
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atl1e_dma_req_512 = 2,
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atl1e_dma_req_1024 = 3,
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atl1e_dma_req_2048 = 4,
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atl1e_dma_req_4096 = 5
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};
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enum atl1e_rrs_type {
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atl1e_rrs_disable = 0,
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atl1e_rrs_ipv4 = 1,
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atl1e_rrs_ipv4_tcp = 2,
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atl1e_rrs_ipv6 = 4,
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atl1e_rrs_ipv6_tcp = 8
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};
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enum atl1e_nic_type {
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athr_l1e = 0,
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athr_l2e_revA = 1,
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athr_l2e_revB = 2
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};
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struct atl1e_hw_stats {
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/* rx */
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unsigned long rx_ok; /* The number of good packet received. */
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unsigned long rx_bcast; /* The number of good broadcast packet received. */
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unsigned long rx_mcast; /* The number of good multicast packet received. */
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unsigned long rx_pause; /* The number of Pause packet received. */
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unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
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unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
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unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
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unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
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unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
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unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
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unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
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unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
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unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
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unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
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unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
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unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
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unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
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unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
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unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
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unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
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unsigned long rx_align_err; /* Alignment Error */
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unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
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unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
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unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
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/* tx */
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unsigned long tx_ok; /* The number of good packet transmitted. */
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unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
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unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
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unsigned long tx_pause; /* The number of Pause packet transmitted. */
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unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
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unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
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unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
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unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
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unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
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unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
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unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
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unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
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unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
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unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
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unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
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unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
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unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
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unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
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unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
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unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
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unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
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unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
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unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
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unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
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unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
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};
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struct atl1e_hw {
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u8 __iomem *hw_addr; /* inner register address */
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resource_size_t mem_rang;
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struct atl1e_adapter *adapter;
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enum atl1e_nic_type nic_type;
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_id;
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u16 subsystem_vendor_id;
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u8 revision_id;
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u16 pci_cmd_word;
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u8 mac_addr[ETH_ALEN];
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u8 perm_mac_addr[ETH_ALEN];
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u8 preamble_len;
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u16 max_frame_size;
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u16 rx_jumbo_th;
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u16 tx_jumbo_th;
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u16 media_type;
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#define MEDIA_TYPE_AUTO_SENSOR 0
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#define MEDIA_TYPE_100M_FULL 1
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#define MEDIA_TYPE_100M_HALF 2
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#define MEDIA_TYPE_10M_FULL 3
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#define MEDIA_TYPE_10M_HALF 4
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u16 autoneg_advertised;
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#define ADVERTISE_10_HALF 0x0001
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#define ADVERTISE_10_FULL 0x0002
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#define ADVERTISE_100_HALF 0x0004
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#define ADVERTISE_100_FULL 0x0008
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#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
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#define ADVERTISE_1000_FULL 0x0020
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u16 mii_autoneg_adv_reg;
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u16 mii_1000t_ctrl_reg;
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u16 imt; /* Interrupt Moderator timer ( 2us resolution) */
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u16 ict; /* Interrupt Clear timer (2us resolution) */
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u32 smb_timer;
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u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
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interrupt request */
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u16 tpd_thresh;
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u16 rx_count_down; /* 2us resolution */
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u16 tx_count_down;
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u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
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enum atl1e_rrs_type rrs_type;
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u32 base_cpu;
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u32 indirect_tab;
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enum atl1e_dma_req_block dmar_block;
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enum atl1e_dma_req_block dmaw_block;
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u8 dmaw_dly_cnt;
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u8 dmar_dly_cnt;
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bool phy_configured;
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bool re_autoneg;
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bool emi_ca;
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};
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/*
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* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer
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*/
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struct atl1e_tx_buffer {
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struct sk_buff *skb;
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u16 flags;
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#define ATL1E_TX_PCIMAP_SINGLE 0x0001
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#define ATL1E_TX_PCIMAP_PAGE 0x0002
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#define ATL1E_TX_PCIMAP_TYPE_MASK 0x0003
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u16 length;
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dma_addr_t dma;
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};
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#define ATL1E_SET_PCIMAP_TYPE(tx_buff, type) do { \
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((tx_buff)->flags) &= ~ATL1E_TX_PCIMAP_TYPE_MASK; \
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((tx_buff)->flags) |= (type); \
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} while (0)
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struct atl1e_rx_page {
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dma_addr_t dma; /* receive rage DMA address */
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u8 *addr; /* receive rage virtual address */
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dma_addr_t write_offset_dma; /* the DMA address which contain the
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receive data offset in the page */
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u32 *write_offset_addr; /* the virtaul address which contain
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the receive data offset in the page */
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u32 read_offset; /* the offset where we have read */
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};
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struct atl1e_rx_page_desc {
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struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE];
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u8 rx_using;
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u16 rx_nxseq;
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};
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/* transmit packet descriptor (tpd) ring */
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struct atl1e_tx_ring {
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struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 count; /* the count of transmit rings */
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rwlock_t tx_lock;
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u16 next_to_use;
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atomic_t next_to_clean;
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struct atl1e_tx_buffer *tx_buffer;
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dma_addr_t cmb_dma;
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u32 *cmb;
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};
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/* receive packet descriptor ring */
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struct atl1e_rx_ring {
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void *desc;
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dma_addr_t dma;
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int size;
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u32 page_size; /* bytes length of rxf page */
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u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
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struct atl1e_rx_page_desc rx_page_desc[AT_MAX_RECEIVE_QUEUE];
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};
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/* board specific private data structure */
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struct atl1e_adapter {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct napi_struct napi;
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struct mii_if_info mii; /* MII interface info */
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struct atl1e_hw hw;
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struct atl1e_hw_stats hw_stats;
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u32 wol;
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u16 link_speed;
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u16 link_duplex;
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spinlock_t mdio_lock;
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atomic_t irq_sem;
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struct work_struct reset_task;
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struct work_struct link_chg_task;
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struct timer_list watchdog_timer;
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struct timer_list phy_config_timer;
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/* All Descriptor memory */
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dma_addr_t ring_dma;
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void *ring_vir_addr;
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u32 ring_size;
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struct atl1e_tx_ring tx_ring;
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struct atl1e_rx_ring rx_ring;
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int num_rx_queues;
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unsigned long flags;
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#define __AT_TESTING 0x0001
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#define __AT_RESETTING 0x0002
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#define __AT_DOWN 0x0003
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u32 bd_number; /* board number;*/
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u32 pci_state[16];
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u32 *config_space;
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};
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#define AT_WRITE_REG(a, reg, value) ( \
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writel((value), ((a)->hw_addr + reg)))
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#define AT_WRITE_FLUSH(a) (\
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readl((a)->hw_addr))
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#define AT_READ_REG(a, reg) ( \
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readl((a)->hw_addr + reg))
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#define AT_WRITE_REGB(a, reg, value) (\
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writeb((value), ((a)->hw_addr + reg)))
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#define AT_READ_REGB(a, reg) (\
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readb((a)->hw_addr + reg))
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#define AT_WRITE_REGW(a, reg, value) (\
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writew((value), ((a)->hw_addr + reg)))
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#define AT_READ_REGW(a, reg) (\
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readw((a)->hw_addr + reg))
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#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
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#define AT_READ_REG_ARRAY(a, reg, offset) ( \
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readl(((a)->hw_addr + reg) + ((offset) << 2)))
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extern char atl1e_driver_name[];
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void atl1e_check_options(struct atl1e_adapter *adapter);
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int atl1e_up(struct atl1e_adapter *adapter);
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void atl1e_down(struct atl1e_adapter *adapter);
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void atl1e_reinit_locked(struct atl1e_adapter *adapter);
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s32 atl1e_reset_hw(struct atl1e_hw *hw);
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void atl1e_set_ethtool_ops(struct net_device *netdev);
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#endif /* _ATL1_E_H_ */
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