afeae6ef07
Enable no tz FW loading and add routine to reset XTSS. Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
161 lines
4.9 KiB
C
161 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
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* Copyright (C) 2017 Linaro Ltd.
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*/
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#ifndef __VENUS_HFI_VENUS_IO_H__
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#define __VENUS_HFI_VENUS_IO_H__
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#define VBIF_BASE 0x80000
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#define VBIF_AXI_HALT_CTRL0 0x208
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#define VBIF_AXI_HALT_CTRL1 0x20c
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#define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
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#define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
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#define VBIF_AXI_HALT_ACK_TIMEOUT_US 500000
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#define CPU_BASE 0xc0000
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#define CPU_CS_BASE (CPU_BASE + 0x12000)
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#define CPU_IC_BASE (CPU_BASE + 0x1f000)
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#define CPU_BASE_V6 0xa0000
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#define CPU_CS_BASE_V6 CPU_BASE_V6
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#define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
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#define CPU_CS_A2HSOFTINTCLR 0x1c
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#define VIDC_CTRL_INIT 0x48
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#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe
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#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1
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#define VIDC_CTRL_INIT_CTRL_MASK 0x1
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#define VIDC_CTRL_INIT_CTRL_SHIFT 0
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/* HFI control status */
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#define CPU_CS_SCIACMDARG0 0x4c
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#define CPU_CS_SCIACMDARG0_MASK 0xff
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#define CPU_CS_SCIACMDARG0_SHIFT 0x0
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#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe
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#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1
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#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1
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#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x0
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#define CPU_CS_SCIACMDARG0_PC_READY BIT(8)
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#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)
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/* HFI queue table info */
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#define CPU_CS_SCIACMDARG1 0x50
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/* HFI queue table address */
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#define CPU_CS_SCIACMDARG2 0x54
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/* Venus cpu */
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#define CPU_CS_SCIACMDARG3 0x58
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#define SFR_ADDR 0x5c
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#define MMAP_ADDR 0x60
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#define UC_REGION_ADDR 0x64
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#define UC_REGION_SIZE 0x68
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#define CPU_CS_H2XSOFTINTEN_V6 0x148
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#define CPU_CS_X2RPMH_V6 0x168
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#define CPU_CS_X2RPMH_MASK0_BMSK_V6 0x1
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#define CPU_CS_X2RPMH_MASK0_SHFT_V6 0x0
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#define CPU_CS_X2RPMH_MASK1_BMSK_V6 0x2
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#define CPU_CS_X2RPMH_MASK1_SHFT_V6 0x1
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#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6 0x4
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#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6 0x3
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/* Relative to CPU_IC_BASE */
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#define CPU_IC_SOFTINT 0x18
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#define CPU_IC_SOFTINT_V6 0x150
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#define CPU_IC_SOFTINT_H2A_MASK 0x8000
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#define CPU_IC_SOFTINT_H2A_SHIFT 0xf
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#define CPU_IC_SOFTINT_H2A_SHIFT_V6 0x0
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/* Venus wrapper */
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#define WRAPPER_BASE_V6 0x000b0000
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#define WRAPPER_BASE 0x000e0000
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#define WRAPPER_HW_VERSION 0x00
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#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000
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#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28
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#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
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#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16
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#define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff
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#define WRAPPER_CLOCK_CONFIG 0x04
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#define WRAPPER_INTR_STATUS 0x0c
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#define WRAPPER_INTR_STATUS_A2HWD_MASK 0x10
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#define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_STATUS_A2H_MASK 0x4
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#define WRAPPER_INTR_STATUS_A2H_SHIFT 0x2
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#define WRAPPER_INTR_MASK 0x10
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#define WRAPPER_INTR_MASK_A2HWD_BASK 0x10
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#define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x8
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#define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3
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#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4
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#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2
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#define WRAPPER_INTR_STATUS_A2HWD_MASK_V6 0x8
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#define WRAPPER_INTR_MASK_A2HWD_BASK_V6 0x8
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#define WRAPPER_INTR_CLEAR 0x14
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#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10
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#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_CLEAR_A2H_MASK 0x4
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#define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2
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#define WRAPPER_POWER_STATUS 0x44
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#define WRAPPER_VDEC_VCODEC_POWER_CONTROL 0x48
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#define WRAPPER_VENC_VCODEC_POWER_CONTROL 0x4c
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#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6 0x54
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#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6 0x58
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#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64
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#define WRAPPER_CPU_CLOCK_CONFIG 0x2000
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#define WRAPPER_CPU_AXI_HALT 0x2008
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#define WRAPPER_CPU_AXI_HALT_HALT BIT(16)
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#define WRAPPER_CPU_AXI_HALT_STATUS 0x200c
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#define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24)
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#define WRAPPER_CPU_CGC_DIS 0x2010
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#define WRAPPER_CPU_STATUS 0x2014
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#define WRAPPER_CPU_STATUS_WFI BIT(0)
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#define WRAPPER_SW_RESET 0x3000
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#define WRAPPER_CPA_START_ADDR 0x1020
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#define WRAPPER_CPA_END_ADDR 0x1024
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#define WRAPPER_FW_START_ADDR 0x1028
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#define WRAPPER_FW_END_ADDR 0x102C
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#define WRAPPER_NONPIX_START_ADDR 0x1030
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#define WRAPPER_NONPIX_END_ADDR 0x1034
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#define WRAPPER_A9SS_SW_RESET 0x3000
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#define WRAPPER_A9SS_SW_RESET_BIT BIT(4)
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/* Venus 4xx */
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#define WRAPPER_VCODEC0_MMCC_POWER_STATUS 0x90
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#define WRAPPER_VCODEC0_MMCC_POWER_CONTROL 0x94
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#define WRAPPER_VCODEC1_MMCC_POWER_STATUS 0x110
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#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL 0x114
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/* Venus 6xx */
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#define WRAPPER_CORE_POWER_STATUS_V6 0x80
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#define WRAPPER_CORE_POWER_CONTROL_V6 0x84
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/* Wrapper TZ 6xx */
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#define WRAPPER_TZ_BASE_V6 0x000c0000
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#define WRAPPER_TZ_CPU_STATUS_V6 0x10
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#define WRAPPER_TZ_XTSS_SW_RESET 0x1000
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#define WRAPPER_XTSS_SW_RESET_BIT BIT(0)
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/* Venus AON */
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#define AON_BASE_V6 0x000e0000
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#define AON_WRAPPER_MVP_NOC_LPI_CONTROL 0x00
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#define AON_WRAPPER_MVP_NOC_LPI_STATUS 0x04
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#endif
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