5f60d5f6bb
asm/unaligned.h is always an include of asm-generic/unaligned.h; might as well move that thing to linux/unaligned.h and include that - there's nothing arch-specific in that header. auto-generated by the following: for i in `git grep -l -w asm/unaligned.h`; do sed -i -e "s/asm\/unaligned.h/linux\/unaligned.h/" $i done for i in `git grep -l -w asm-generic/unaligned.h`; do sed -i -e "s/asm-generic\/unaligned.h/linux\/unaligned.h/" $i done git mv include/asm-generic/unaligned.h include/linux/unaligned.h git mv tools/include/asm-generic/unaligned.h tools/include/linux/unaligned.h sed -i -e "/unaligned.h/d" include/asm-generic/Kbuild sed -i -e "s/__ASM_GENERIC/__LINUX/" include/linux/unaligned.h tools/include/linux/unaligned.h
1021 lines
26 KiB
C
1021 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Linaro Limited.
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* Author: Caleb Connolly <caleb.connolly@linaro.org>
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*
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* This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs.
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/spmi.h>
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#include <linux/types.h>
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#include <linux/units.h>
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#include <linux/unaligned.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/types.h>
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#include <soc/qcom/qcom-spmi-pmic.h>
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#define DRIVER_NAME "qcom-spmi-rradc"
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#define RR_ADC_EN_CTL 0x46
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#define RR_ADC_SKIN_TEMP_LSB 0x50
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#define RR_ADC_SKIN_TEMP_MSB 0x51
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#define RR_ADC_CTL 0x52
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#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3)
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#define RR_ADC_LOG 0x53
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#define RR_ADC_LOG_CLR_CTRL BIT(0)
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#define RR_ADC_FAKE_BATT_LOW_LSB 0x58
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#define RR_ADC_FAKE_BATT_LOW_MSB 0x59
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#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
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#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
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#define RR_ADC_BATT_ID_CTRL 0x60
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#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
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#define RR_ADC_BATT_ID_TRIGGER 0x61
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#define RR_ADC_BATT_ID_STS 0x62
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#define RR_ADC_BATT_ID_CFG 0x63
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#define BATT_ID_SETTLE_MASK GENMASK(7, 5)
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#define RR_ADC_BATT_ID_5_LSB 0x66
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#define RR_ADC_BATT_ID_5_MSB 0x67
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#define RR_ADC_BATT_ID_15_LSB 0x68
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#define RR_ADC_BATT_ID_15_MSB 0x69
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#define RR_ADC_BATT_ID_150_LSB 0x6A
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#define RR_ADC_BATT_ID_150_MSB 0x6B
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#define RR_ADC_BATT_THERM_CTRL 0x70
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#define RR_ADC_BATT_THERM_TRIGGER 0x71
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#define RR_ADC_BATT_THERM_STS 0x72
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#define RR_ADC_BATT_THERM_CFG 0x73
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#define RR_ADC_BATT_THERM_LSB 0x74
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#define RR_ADC_BATT_THERM_MSB 0x75
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#define RR_ADC_BATT_THERM_FREQ 0x76
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#define RR_ADC_AUX_THERM_CTRL 0x80
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#define RR_ADC_AUX_THERM_TRIGGER 0x81
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#define RR_ADC_AUX_THERM_STS 0x82
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#define RR_ADC_AUX_THERM_CFG 0x83
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#define RR_ADC_AUX_THERM_LSB 0x84
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#define RR_ADC_AUX_THERM_MSB 0x85
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#define RR_ADC_SKIN_HOT 0x86
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#define RR_ADC_SKIN_TOO_HOT 0x87
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#define RR_ADC_AUX_THERM_C1 0x88
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#define RR_ADC_AUX_THERM_C2 0x89
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#define RR_ADC_AUX_THERM_C3 0x8A
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#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
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#define RR_ADC_USB_IN_V_CTRL 0x90
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#define RR_ADC_USB_IN_V_TRIGGER 0x91
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#define RR_ADC_USB_IN_V_STS 0x92
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#define RR_ADC_USB_IN_V_LSB 0x94
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#define RR_ADC_USB_IN_V_MSB 0x95
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#define RR_ADC_USB_IN_I_CTRL 0x98
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#define RR_ADC_USB_IN_I_TRIGGER 0x99
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#define RR_ADC_USB_IN_I_STS 0x9A
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#define RR_ADC_USB_IN_I_LSB 0x9C
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#define RR_ADC_USB_IN_I_MSB 0x9D
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#define RR_ADC_DC_IN_V_CTRL 0xA0
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#define RR_ADC_DC_IN_V_TRIGGER 0xA1
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#define RR_ADC_DC_IN_V_STS 0xA2
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#define RR_ADC_DC_IN_V_LSB 0xA4
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#define RR_ADC_DC_IN_V_MSB 0xA5
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#define RR_ADC_DC_IN_I_CTRL 0xA8
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#define RR_ADC_DC_IN_I_TRIGGER 0xA9
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#define RR_ADC_DC_IN_I_STS 0xAA
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#define RR_ADC_DC_IN_I_LSB 0xAC
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#define RR_ADC_DC_IN_I_MSB 0xAD
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#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
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#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
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#define RR_ADC_PMI_DIE_TEMP_STS 0xB2
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#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
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#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
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#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
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#define RR_ADC_CHARGER_TEMP_CTRL 0xB8
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#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
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#define RR_ADC_CHARGER_TEMP_STS 0xBA
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#define RR_ADC_CHARGER_TEMP_CFG 0xBB
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#define RR_ADC_CHARGER_TEMP_LSB 0xBC
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#define RR_ADC_CHARGER_TEMP_MSB 0xBD
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#define RR_ADC_CHARGER_HOT 0xBE
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#define RR_ADC_CHARGER_TOO_HOT 0xBF
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#define RR_ADC_GPIO_CTRL 0xC0
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#define RR_ADC_GPIO_TRIGGER 0xC1
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#define RR_ADC_GPIO_STS 0xC2
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#define RR_ADC_GPIO_LSB 0xC4
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#define RR_ADC_GPIO_MSB 0xC5
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#define RR_ADC_ATEST_CTRL 0xC8
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#define RR_ADC_ATEST_TRIGGER 0xC9
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#define RR_ADC_ATEST_STS 0xCA
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#define RR_ADC_ATEST_LSB 0xCC
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#define RR_ADC_ATEST_MSB 0xCD
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#define RR_ADC_SEC_ACCESS 0xD0
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#define RR_ADC_PERPH_RESET_CTL2 0xD9
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#define RR_ADC_PERPH_RESET_CTL3 0xDA
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#define RR_ADC_PERPH_RESET_CTL4 0xDB
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#define RR_ADC_INT_TEST1 0xE0
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#define RR_ADC_INT_TEST_VAL 0xE1
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#define RR_ADC_TM_TRIGGER_CTRLS 0xE2
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#define RR_ADC_TM_ADC_CTRLS 0xE3
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#define RR_ADC_TM_CNL_CTRL 0xE4
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#define RR_ADC_TM_BATT_ID_CTRL 0xE5
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#define RR_ADC_TM_THERM_CTRL 0xE6
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#define RR_ADC_TM_CONV_STS 0xE7
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#define RR_ADC_TM_ADC_READ_LSB 0xE8
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#define RR_ADC_TM_ADC_READ_MSB 0xE9
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#define RR_ADC_TM_ATEST_MUX_1 0xEA
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#define RR_ADC_TM_ATEST_MUX_2 0xEB
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#define RR_ADC_TM_REFERENCES 0xED
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#define RR_ADC_TM_MISC_CTL 0xEE
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#define RR_ADC_TM_RR_CTRL 0xEF
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#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7)
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#define RR_ADC_TRIGGER_CTL BIT(0)
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#define RR_ADC_BATT_ID_RANGE 820
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#define RR_ADC_BITS 10
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#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS)
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#define RR_ADC_FS_VOLTAGE_MV 2500
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/* BATT_THERM 0.25K/LSB */
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#define RR_ADC_BATT_THERM_LSB_K 4
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#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000
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#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3
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#define RR_ADC_DIE_TEMP_OFFSET 601400
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#define RR_ADC_DIE_TEMP_SLOPE 2
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#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000
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#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168
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#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
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#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433
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#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655
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#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001
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#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403
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#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898
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#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596
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#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779
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#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496
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#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000
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#define RR_ADC_CHG_THRESHOLD_SCALE 4
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#define RR_ADC_VOLT_INPUT_FACTOR 8
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#define RR_ADC_CURR_INPUT_FACTOR 2000
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#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886
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#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9
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#define RR_ADC_CURR_USBIN_660_UV_VAL 579500
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#define RR_ADC_GPIO_FS_RANGE 5000
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#define RR_ADC_COHERENT_CHECK_RETRY 5
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#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16
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#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)
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#define RR_ADC_STS_CHANNEL_STS BIT(1)
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#define RR_ADC_TP_REV_VERSION1 21
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#define RR_ADC_TP_REV_VERSION2 29
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#define RR_ADC_TP_REV_VERSION3 32
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#define RRADC_BATT_ID_DELAY_MAX 8
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enum rradc_channel_id {
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RR_ADC_BATT_ID = 0,
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RR_ADC_BATT_THERM,
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RR_ADC_SKIN_TEMP,
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RR_ADC_USBIN_I,
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RR_ADC_USBIN_V,
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RR_ADC_DCIN_I,
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RR_ADC_DCIN_V,
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RR_ADC_DIE_TEMP,
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RR_ADC_CHG_TEMP,
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RR_ADC_GPIO,
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RR_ADC_CHAN_MAX
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};
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struct rradc_chip;
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/**
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* struct rradc_channel - rradc channel data
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* @label: channel label
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* @lsb: Channel least significant byte
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* @status: Channel status address
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* @size: number of bytes to read
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* @trigger_addr: Trigger address, trigger is only used on some channels
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* @trigger_mask: Trigger mask
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* @scale_fn: Post process callback for channels which can't be exposed
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* as offset + scale.
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*/
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struct rradc_channel {
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const char *label;
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u8 lsb;
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u8 status;
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int size;
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int trigger_addr;
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int trigger_mask;
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int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result);
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};
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struct rradc_chip {
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struct device *dev;
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const struct qcom_spmi_pmic *pmic;
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/*
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* Lock held while doing channel conversion
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* involving multiple register read/writes
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*/
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struct mutex conversion_lock;
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struct regmap *regmap;
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u32 base;
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int batt_id_delay;
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u16 batt_id_data;
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};
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static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
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static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX];
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static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX];
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static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len)
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{
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int ret, retry_cnt = 0;
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__le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2];
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if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) {
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dev_err(chip->dev,
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"Can't read more than %d bytes, but asked to read %d bytes.\n",
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RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len);
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return -EINVAL;
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}
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while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) {
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ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf,
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len);
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if (ret < 0) {
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dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
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ret);
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return ret;
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}
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ret = regmap_bulk_read(chip->regmap, chip->base + addr,
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data_check, len);
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if (ret < 0) {
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dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
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ret);
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return ret;
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}
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if (memcmp(buf, data_check, len) != 0) {
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retry_cnt++;
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dev_dbg(chip->dev,
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"coherent read error, retry_cnt:%d\n",
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retry_cnt);
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continue;
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}
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break;
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}
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if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY)
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dev_err(chip->dev, "Retry exceeded for coherency check\n");
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return ret;
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}
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static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset,
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int64_t *slope)
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{
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if (chip->pmic->subtype == PM660_SUBTYPE) {
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switch (chip->pmic->fab_id) {
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case PM660_FAB_ID_GF:
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*offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV;
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*slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
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return 0;
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case PM660_FAB_ID_TSMC:
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*offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV;
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*slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
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return 0;
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default:
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*offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV;
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*slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C;
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}
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} else if (chip->pmic->subtype == PMI8998_SUBTYPE) {
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switch (chip->pmic->fab_id) {
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case PMI8998_FAB_ID_GF:
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*offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV;
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*slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C;
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return 0;
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case PMI8998_FAB_ID_SMIC:
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*offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV;
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*slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
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return 0;
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default:
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return -EINVAL;
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}
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}
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return -EINVAL;
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}
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/*
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* These functions explicitly cast int64_t to int.
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* They will never overflow, as the values are small enough.
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*/
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static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code,
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int *result_ohms)
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{
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uint32_t current_value;
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int64_t r_id;
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current_value = chip->batt_id_data;
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r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV);
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r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value));
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*result_ohms = (int)(r_id * MILLI);
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return 0;
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}
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static int rradc_enable_continuous_mode(struct rradc_chip *chip)
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{
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int ret;
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/* Clear channel log */
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ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_LOG,
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RR_ADC_LOG_CLR_CTRL);
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if (ret < 0) {
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dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);
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return ret;
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}
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ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_LOG,
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RR_ADC_LOG_CLR_CTRL);
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if (ret < 0) {
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dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",
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ret);
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return ret;
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}
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/* Switch to continuous mode */
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ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_CTL,
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RR_ADC_CTL_CONTINUOUS_SEL);
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if (ret < 0)
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dev_err(chip->dev, "Update to continuous mode failed:%d\n",
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ret);
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return ret;
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}
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static int rradc_disable_continuous_mode(struct rradc_chip *chip)
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{
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int ret;
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/* Switch to non continuous mode */
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ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_CTL,
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RR_ADC_CTL_CONTINUOUS_SEL);
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if (ret < 0)
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dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",
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ret);
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return ret;
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}
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static bool rradc_is_ready(struct rradc_chip *chip,
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enum rradc_channel_id chan_address)
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{
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const struct rradc_channel *chan = &rradc_chans[chan_address];
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int ret;
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unsigned int status, mask;
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/* BATT_ID STS bit does not get set initially */
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switch (chan_address) {
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case RR_ADC_BATT_ID:
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mask = RR_ADC_STS_CHANNEL_STS;
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break;
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default:
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mask = RR_ADC_STS_CHANNEL_READING_MASK;
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break;
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}
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ret = regmap_read(chip->regmap, chip->base + chan->status, &status);
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if (ret < 0 || !(status & mask))
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return false;
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return true;
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}
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static int rradc_read_status_in_cont_mode(struct rradc_chip *chip,
|
|
enum rradc_channel_id chan_address)
|
|
{
|
|
const struct rradc_channel *chan = &rradc_chans[chan_address];
|
|
const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
|
|
int ret, i;
|
|
|
|
if (chan->trigger_mask == 0) {
|
|
dev_err(chip->dev, "Channel doesn't have a trigger mask\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = regmap_set_bits(chip->regmap, chip->base + chan->trigger_addr,
|
|
chan->trigger_mask);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev,
|
|
"Failed to apply trigger for channel '%s' ret=%d\n",
|
|
iio_chan->extend_name, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = rradc_enable_continuous_mode(chip);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Failed to switch to continuous mode\n");
|
|
goto disable_trigger;
|
|
}
|
|
|
|
/*
|
|
* The wait/sleep values were found through trial and error,
|
|
* this is mostly for the battery ID channel which takes some
|
|
* time to settle.
|
|
*/
|
|
for (i = 0; i < 5; i++) {
|
|
if (rradc_is_ready(chip, chan_address))
|
|
break;
|
|
usleep_range(50000, 50000 + 500);
|
|
}
|
|
|
|
if (i == 5) {
|
|
dev_err(chip->dev, "Channel '%s' is not ready\n",
|
|
iio_chan->extend_name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
rradc_disable_continuous_mode(chip);
|
|
|
|
disable_trigger:
|
|
regmap_clear_bits(chip->regmap, chip->base + chan->trigger_addr,
|
|
chan->trigger_mask);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip,
|
|
enum rradc_channel_id chan_address,
|
|
u16 *data)
|
|
{
|
|
int ret;
|
|
|
|
ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
|
|
RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regmap_set_bits(chip->regmap,
|
|
chip->base + RR_ADC_BATT_ID_TRIGGER,
|
|
RR_ADC_TRIGGER_CTL);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);
|
|
goto out_disable_batt_id;
|
|
}
|
|
|
|
ret = rradc_read_status_in_cont_mode(chip, chan_address);
|
|
|
|
/* Reset registers back to default values */
|
|
regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER,
|
|
RR_ADC_TRIGGER_CTL);
|
|
|
|
out_disable_batt_id:
|
|
regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
|
|
RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rradc_do_conversion(struct rradc_chip *chip,
|
|
enum rradc_channel_id chan_address, u16 *data)
|
|
{
|
|
const struct rradc_channel *chan = &rradc_chans[chan_address];
|
|
const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
|
|
int ret;
|
|
__le16 buf[3];
|
|
|
|
mutex_lock(&chip->conversion_lock);
|
|
|
|
switch (chan_address) {
|
|
case RR_ADC_BATT_ID:
|
|
ret = rradc_prepare_batt_id_conversion(chip, chan_address, data);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Battery ID conversion failed:%d\n",
|
|
ret);
|
|
goto unlock_out;
|
|
}
|
|
break;
|
|
|
|
case RR_ADC_USBIN_V:
|
|
case RR_ADC_DIE_TEMP:
|
|
ret = rradc_read_status_in_cont_mode(chip, chan_address);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev,
|
|
"Error reading in continuous mode:%d\n", ret);
|
|
goto unlock_out;
|
|
}
|
|
break;
|
|
default:
|
|
if (!rradc_is_ready(chip, chan_address)) {
|
|
/*
|
|
* Usually this means the channel isn't attached, for example
|
|
* the in_voltage_usbin_v_input channel will not be ready if
|
|
* no USB cable is attached
|
|
*/
|
|
dev_dbg(chip->dev, "channel '%s' is not ready\n",
|
|
iio_chan->extend_name);
|
|
ret = -ENODATA;
|
|
goto unlock_out;
|
|
}
|
|
break;
|
|
}
|
|
|
|
ret = rradc_read(chip, chan->lsb, buf, chan->size);
|
|
if (ret) {
|
|
dev_err(chip->dev, "read data failed\n");
|
|
goto unlock_out;
|
|
}
|
|
|
|
/*
|
|
* For the battery ID we read the register for every ID ADC and then
|
|
* see which one is actually connected.
|
|
*/
|
|
if (chan_address == RR_ADC_BATT_ID) {
|
|
u16 batt_id_150 = le16_to_cpu(buf[2]);
|
|
u16 batt_id_15 = le16_to_cpu(buf[1]);
|
|
u16 batt_id_5 = le16_to_cpu(buf[0]);
|
|
|
|
if (!batt_id_150 && !batt_id_15 && !batt_id_5) {
|
|
dev_err(chip->dev,
|
|
"Invalid batt_id values with all zeros\n");
|
|
ret = -EINVAL;
|
|
goto unlock_out;
|
|
}
|
|
|
|
if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) {
|
|
*data = batt_id_150;
|
|
chip->batt_id_data = 150;
|
|
} else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) {
|
|
*data = batt_id_15;
|
|
chip->batt_id_data = 15;
|
|
} else {
|
|
*data = batt_id_5;
|
|
chip->batt_id_data = 5;
|
|
}
|
|
} else {
|
|
/*
|
|
* All of the other channels are either 1 or 2 bytes.
|
|
* We can rely on the second byte being 0 for 1-byte channels.
|
|
*/
|
|
*data = le16_to_cpu(buf[0]);
|
|
}
|
|
|
|
unlock_out:
|
|
mutex_unlock(&chip->conversion_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val,
|
|
int *val2)
|
|
{
|
|
int64_t fab_offset, fab_slope;
|
|
int ret;
|
|
|
|
ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Unable to get fab id coefficients\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (chan_address) {
|
|
case RR_ADC_SKIN_TEMP:
|
|
*val = MILLI;
|
|
*val2 = RR_ADC_BATT_THERM_LSB_K;
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_USBIN_I:
|
|
*val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL *
|
|
RR_ADC_FS_VOLTAGE_MV;
|
|
*val2 = RR_ADC_CHAN_MSB;
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_DCIN_I:
|
|
*val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV;
|
|
*val2 = RR_ADC_CHAN_MSB;
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_USBIN_V:
|
|
case RR_ADC_DCIN_V:
|
|
*val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI;
|
|
*val2 = RR_ADC_CHAN_MSB;
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_GPIO:
|
|
*val = RR_ADC_GPIO_FS_RANGE;
|
|
*val2 = RR_ADC_CHAN_MSB;
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_CHG_TEMP:
|
|
/*
|
|
* We divide val2 by MILLI instead of multiplying val
|
|
* to avoid an integer overflow.
|
|
*/
|
|
*val = -RR_ADC_TEMP_FS_VOLTAGE_NUM;
|
|
*val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
|
|
fab_slope,
|
|
MILLI);
|
|
|
|
return IIO_VAL_FRACTIONAL;
|
|
case RR_ADC_DIE_TEMP:
|
|
*val = RR_ADC_TEMP_FS_VOLTAGE_NUM;
|
|
*val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
|
|
RR_ADC_DIE_TEMP_SLOPE;
|
|
|
|
return IIO_VAL_FRACTIONAL;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val)
|
|
{
|
|
int64_t fab_offset, fab_slope;
|
|
int64_t offset1, offset2;
|
|
int ret;
|
|
|
|
switch (chan_address) {
|
|
case RR_ADC_SKIN_TEMP:
|
|
/*
|
|
* Offset from kelvin to degC, divided by the
|
|
* scale factor (250). We lose some precision here.
|
|
* 273150 / 250 = 1092.6
|
|
*/
|
|
*val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS,
|
|
(MILLI / RR_ADC_BATT_THERM_LSB_K));
|
|
return IIO_VAL_INT;
|
|
case RR_ADC_CHG_TEMP:
|
|
ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev,
|
|
"Unable to get fab id coefficients\n");
|
|
return -EINVAL;
|
|
}
|
|
offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN *
|
|
RR_ADC_CHAN_MSB);
|
|
offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL;
|
|
offset1 = div64_s64(offset1,
|
|
(int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM));
|
|
|
|
offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
|
|
RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
|
|
(int64_t)fab_slope;
|
|
offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2;
|
|
offset2 = div64_s64(
|
|
offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM));
|
|
|
|
/*
|
|
* The -1 is to compensate for lost precision.
|
|
* It should actually be -0.7906976744186046.
|
|
* This works out to every value being off
|
|
* by about +0.091 degrees C after applying offset and scale.
|
|
*/
|
|
*val = (int)(offset1 - offset2 - 1);
|
|
return IIO_VAL_INT;
|
|
case RR_ADC_DIE_TEMP:
|
|
offset1 = -RR_ADC_DIE_TEMP_OFFSET *
|
|
(int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN *
|
|
(int64_t)RR_ADC_CHAN_MSB;
|
|
offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM);
|
|
|
|
offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
|
|
RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
|
|
RR_ADC_DIE_TEMP_SLOPE;
|
|
offset2 = div64_s64(offset2,
|
|
((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM));
|
|
|
|
/*
|
|
* The result is -339, it should be -338.69789, this results
|
|
* in the calculated die temp being off by
|
|
* -0.004 - -0.0175 degrees C
|
|
*/
|
|
*val = (int)(offset1 - offset2);
|
|
return IIO_VAL_INT;
|
|
default:
|
|
break;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int rradc_read_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan_spec, int *val,
|
|
int *val2, long mask)
|
|
{
|
|
struct rradc_chip *chip = iio_priv(indio_dev);
|
|
const struct rradc_channel *chan;
|
|
int ret;
|
|
u16 adc_code;
|
|
|
|
if (chan_spec->address >= RR_ADC_CHAN_MAX) {
|
|
dev_err(chip->dev, "Invalid channel index:%lu\n",
|
|
chan_spec->address);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SCALE:
|
|
return rradc_read_scale(chip, chan_spec->address, val, val2);
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
return rradc_read_offset(chip, chan_spec->address, val);
|
|
case IIO_CHAN_INFO_RAW:
|
|
ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*val = adc_code;
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_PROCESSED:
|
|
chan = &rradc_chans[chan_spec->address];
|
|
if (!chan->scale_fn)
|
|
return -EINVAL;
|
|
ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*val = chan->scale_fn(chip, adc_code, val);
|
|
return IIO_VAL_INT;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int rradc_read_label(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan, char *label)
|
|
{
|
|
return snprintf(label, PAGE_SIZE, "%s\n",
|
|
rradc_chans[chan->address].label);
|
|
}
|
|
|
|
static const struct iio_info rradc_info = {
|
|
.read_raw = rradc_read_raw,
|
|
.read_label = rradc_read_label,
|
|
};
|
|
|
|
static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = {
|
|
{
|
|
.label = "batt_id",
|
|
.scale_fn = rradc_post_process_batt_id,
|
|
.lsb = RR_ADC_BATT_ID_5_LSB,
|
|
.status = RR_ADC_BATT_ID_STS,
|
|
.size = 6,
|
|
.trigger_addr = RR_ADC_BATT_ID_TRIGGER,
|
|
.trigger_mask = BIT(0),
|
|
}, {
|
|
.label = "batt",
|
|
.lsb = RR_ADC_BATT_THERM_LSB,
|
|
.status = RR_ADC_BATT_THERM_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_BATT_THERM_TRIGGER,
|
|
}, {
|
|
.label = "pmi8998_skin",
|
|
.lsb = RR_ADC_SKIN_TEMP_LSB,
|
|
.status = RR_ADC_AUX_THERM_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
|
|
}, {
|
|
.label = "usbin_i",
|
|
.lsb = RR_ADC_USB_IN_I_LSB,
|
|
.status = RR_ADC_USB_IN_I_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_USB_IN_I_TRIGGER,
|
|
}, {
|
|
.label = "usbin_v",
|
|
.lsb = RR_ADC_USB_IN_V_LSB,
|
|
.status = RR_ADC_USB_IN_V_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_USB_IN_V_TRIGGER,
|
|
.trigger_mask = BIT(7),
|
|
}, {
|
|
.label = "dcin_i",
|
|
.lsb = RR_ADC_DC_IN_I_LSB,
|
|
.status = RR_ADC_DC_IN_I_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_DC_IN_I_TRIGGER,
|
|
}, {
|
|
.label = "dcin_v",
|
|
.lsb = RR_ADC_DC_IN_V_LSB,
|
|
.status = RR_ADC_DC_IN_V_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_DC_IN_V_TRIGGER,
|
|
}, {
|
|
.label = "pmi8998_die",
|
|
.lsb = RR_ADC_PMI_DIE_TEMP_LSB,
|
|
.status = RR_ADC_PMI_DIE_TEMP_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER,
|
|
.trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE,
|
|
}, {
|
|
.label = "chg",
|
|
.lsb = RR_ADC_CHARGER_TEMP_LSB,
|
|
.status = RR_ADC_CHARGER_TEMP_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
|
|
}, {
|
|
.label = "gpio",
|
|
.lsb = RR_ADC_GPIO_LSB,
|
|
.status = RR_ADC_GPIO_STS,
|
|
.size = 2,
|
|
.trigger_addr = RR_ADC_GPIO_TRIGGER,
|
|
},
|
|
};
|
|
|
|
static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = {
|
|
{
|
|
.type = IIO_RESISTANCE,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
|
|
.address = RR_ADC_BATT_ID,
|
|
.channel = 0,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_TEMP,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
|
|
.address = RR_ADC_BATT_THERM,
|
|
.channel = 0,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_TEMP,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE) |
|
|
BIT(IIO_CHAN_INFO_OFFSET),
|
|
.address = RR_ADC_SKIN_TEMP,
|
|
.channel = 1,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_CURRENT,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_USBIN_I,
|
|
.channel = 0,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_VOLTAGE,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_USBIN_V,
|
|
.channel = 0,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_CURRENT,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_DCIN_I,
|
|
.channel = 1,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_VOLTAGE,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_DCIN_V,
|
|
.channel = 1,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_TEMP,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_SCALE) |
|
|
BIT(IIO_CHAN_INFO_OFFSET),
|
|
.address = RR_ADC_DIE_TEMP,
|
|
.channel = 2,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_TEMP,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
BIT(IIO_CHAN_INFO_OFFSET) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_CHG_TEMP,
|
|
.channel = 3,
|
|
.indexed = 1,
|
|
}, {
|
|
.type = IIO_VOLTAGE,
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
|
|
BIT(IIO_CHAN_INFO_SCALE),
|
|
.address = RR_ADC_GPIO,
|
|
.channel = 2,
|
|
.indexed = 1,
|
|
},
|
|
};
|
|
|
|
static int rradc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct iio_dev *indio_dev;
|
|
struct rradc_chip *chip;
|
|
int ret, i, batt_id_delay;
|
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
chip = iio_priv(indio_dev);
|
|
chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
|
if (!chip->regmap) {
|
|
dev_err(dev, "Couldn't get parent's regmap\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->dev = dev;
|
|
mutex_init(&chip->conversion_lock);
|
|
|
|
ret = device_property_read_u32(dev, "reg", &chip->base);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
batt_id_delay = -1;
|
|
ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
|
|
&batt_id_delay);
|
|
if (!ret) {
|
|
for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {
|
|
if (batt_id_delay == batt_id_delays[i])
|
|
break;
|
|
}
|
|
if (i == RRADC_BATT_ID_DELAY_MAX)
|
|
batt_id_delay = -1;
|
|
}
|
|
|
|
if (batt_id_delay >= 0) {
|
|
batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay);
|
|
ret = regmap_set_bits(chip->regmap,
|
|
chip->base + RR_ADC_BATT_ID_CFG,
|
|
batt_id_delay);
|
|
if (ret < 0) {
|
|
dev_err(chip->dev,
|
|
"BATT_ID settling time config failed:%d\n",
|
|
ret);
|
|
}
|
|
}
|
|
|
|
/* Get the PMIC revision, we need it to handle some varying coefficients */
|
|
chip->pmic = qcom_pmic_get(chip->dev);
|
|
if (IS_ERR(chip->pmic)) {
|
|
dev_err(chip->dev, "Unable to get reference to PMIC device\n");
|
|
return PTR_ERR(chip->pmic);
|
|
}
|
|
|
|
switch (chip->pmic->subtype) {
|
|
case PMI8998_SUBTYPE:
|
|
indio_dev->name = "pmi8998-rradc";
|
|
break;
|
|
case PM660_SUBTYPE:
|
|
indio_dev->name = "pm660-rradc";
|
|
break;
|
|
default:
|
|
indio_dev->name = DRIVER_NAME;
|
|
break;
|
|
}
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->info = &rradc_info;
|
|
indio_dev->channels = rradc_iio_chans;
|
|
indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans);
|
|
|
|
return devm_iio_device_register(dev, indio_dev);
|
|
}
|
|
|
|
static const struct of_device_id rradc_match_table[] = {
|
|
{ .compatible = "qcom,pm660-rradc" },
|
|
{ .compatible = "qcom,pmi8998-rradc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rradc_match_table);
|
|
|
|
static struct platform_driver rradc_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = rradc_match_table,
|
|
},
|
|
.probe = rradc_probe,
|
|
};
|
|
module_platform_driver(rradc_driver);
|
|
|
|
MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver");
|
|
MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
|
|
MODULE_LICENSE("GPL");
|