09e3bdfe49
This is a frequent minor comment in reviews, so start cleaning up existing drivers in the hope we get fewer cases of cut and paste. There are not kernel wide rules for these, but for IIO the style that I prefer (and hence most common) is: - Space after { and before } - No comma after terminator { } This may cause merge conflicts but they should be trivial to resolve hence I have not broken this into per driver patches. Link: https://patch.msgid.link/20240818180912.719399-1-jic23@kernel.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
650 lines
16 KiB
C
650 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* iio/adc/max1027.c
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* Copyright (C) 2014 Philippe Reynes
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*
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* based on linux/drivers/iio/ad7923.c
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* Copyright 2011 Analog Devices Inc (from AD7923 Driver)
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* Copyright 2012 CS Systemes d'Information
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*
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* max1027.c
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*
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* Partial support for max1027 and similar chips.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define MAX1027_CONV_REG BIT(7)
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#define MAX1027_SETUP_REG BIT(6)
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#define MAX1027_AVG_REG BIT(5)
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#define MAX1027_RST_REG BIT(4)
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/* conversion register */
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#define MAX1027_TEMP BIT(0)
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#define MAX1027_SCAN_0_N (0x00 << 1)
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#define MAX1027_SCAN_N_M (0x01 << 1)
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#define MAX1027_SCAN_N (0x02 << 1)
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#define MAX1027_NOSCAN (0x03 << 1)
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#define MAX1027_CHAN(n) ((n) << 3)
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/* setup register */
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#define MAX1027_UNIPOLAR 0x02
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#define MAX1027_BIPOLAR 0x03
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#define MAX1027_REF_MODE0 (0x00 << 2)
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#define MAX1027_REF_MODE1 (0x01 << 2)
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#define MAX1027_REF_MODE2 (0x02 << 2)
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#define MAX1027_REF_MODE3 (0x03 << 2)
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#define MAX1027_CKS_MODE0 (0x00 << 4)
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#define MAX1027_CKS_MODE1 (0x01 << 4)
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#define MAX1027_CKS_MODE2 (0x02 << 4)
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#define MAX1027_CKS_MODE3 (0x03 << 4)
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/* averaging register */
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#define MAX1027_NSCAN_4 0x00
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#define MAX1027_NSCAN_8 0x01
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#define MAX1027_NSCAN_12 0x02
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#define MAX1027_NSCAN_16 0x03
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#define MAX1027_NAVG_4 (0x00 << 2)
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#define MAX1027_NAVG_8 (0x01 << 2)
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#define MAX1027_NAVG_16 (0x02 << 2)
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#define MAX1027_NAVG_32 (0x03 << 2)
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#define MAX1027_AVG_EN BIT(4)
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/* Device can achieve 300ksps so we assume a 3.33us conversion delay */
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#define MAX1027_CONVERSION_UDELAY 4
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enum max1027_id {
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max1027,
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max1029,
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max1031,
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max1227,
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max1229,
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max1231,
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};
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static const struct spi_device_id max1027_id[] = {
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{ "max1027", max1027 },
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{ "max1029", max1029 },
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{ "max1031", max1031 },
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{ "max1227", max1227 },
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{ "max1229", max1229 },
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{ "max1231", max1231 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, max1027_id);
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static const struct of_device_id max1027_adc_dt_ids[] = {
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{ .compatible = "maxim,max1027" },
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{ .compatible = "maxim,max1029" },
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{ .compatible = "maxim,max1031" },
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{ .compatible = "maxim,max1227" },
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{ .compatible = "maxim,max1229" },
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{ .compatible = "maxim,max1231" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
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#define MAX1027_V_CHAN(index, depth) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = index + 1, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = depth, \
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.storagebits = 16, \
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.shift = (depth == 10) ? 2 : 0, \
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.endianness = IIO_BE, \
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}, \
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}
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#define MAX1027_T_CHAN \
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{ \
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.type = IIO_TEMP, \
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.channel = 0, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = 0, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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.storagebits = 16, \
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.endianness = IIO_BE, \
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}, \
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}
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#define MAX1X27_CHANNELS(depth) \
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MAX1027_T_CHAN, \
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MAX1027_V_CHAN(0, depth), \
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MAX1027_V_CHAN(1, depth), \
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MAX1027_V_CHAN(2, depth), \
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MAX1027_V_CHAN(3, depth), \
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MAX1027_V_CHAN(4, depth), \
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MAX1027_V_CHAN(5, depth), \
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MAX1027_V_CHAN(6, depth), \
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MAX1027_V_CHAN(7, depth)
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#define MAX1X29_CHANNELS(depth) \
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MAX1X27_CHANNELS(depth), \
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MAX1027_V_CHAN(8, depth), \
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MAX1027_V_CHAN(9, depth), \
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MAX1027_V_CHAN(10, depth), \
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MAX1027_V_CHAN(11, depth)
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#define MAX1X31_CHANNELS(depth) \
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MAX1X29_CHANNELS(depth), \
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MAX1027_V_CHAN(12, depth), \
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MAX1027_V_CHAN(13, depth), \
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MAX1027_V_CHAN(14, depth), \
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MAX1027_V_CHAN(15, depth)
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static const struct iio_chan_spec max1027_channels[] = {
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MAX1X27_CHANNELS(10),
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};
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static const struct iio_chan_spec max1029_channels[] = {
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MAX1X29_CHANNELS(10),
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};
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static const struct iio_chan_spec max1031_channels[] = {
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MAX1X31_CHANNELS(10),
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};
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static const struct iio_chan_spec max1227_channels[] = {
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MAX1X27_CHANNELS(12),
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};
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static const struct iio_chan_spec max1229_channels[] = {
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MAX1X29_CHANNELS(12),
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};
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static const struct iio_chan_spec max1231_channels[] = {
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MAX1X31_CHANNELS(12),
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};
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/*
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* These devices are able to scan from 0 to N, N being the highest voltage
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* channel requested by the user. The temperature can be included or not,
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* but cannot be retrieved alone. Based on the below
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* ->available_scan_masks, the core will select the most appropriate
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* ->active_scan_mask and the "minimum" number of channels will be
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* scanned and pushed to the buffers.
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*
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* For example, if the user wants channels 1, 4 and 5, all channels from
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* 0 to 5 will be scanned and pushed to the IIO buffers. The core will then
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* filter out the unneeded samples based on the ->active_scan_mask that has
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* been selected and only channels 1, 4 and 5 will be available to the user
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* in the shared buffer.
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*/
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#define MAX1X27_SCAN_MASK_TEMP BIT(0)
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#define MAX1X27_SCAN_MASKS(temp) \
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GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)), \
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GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)), \
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GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)), \
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GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp))
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#define MAX1X29_SCAN_MASKS(temp) \
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MAX1X27_SCAN_MASKS(temp), \
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GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)), \
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GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp))
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#define MAX1X31_SCAN_MASKS(temp) \
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MAX1X29_SCAN_MASKS(temp), \
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GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)), \
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GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp))
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static const unsigned long max1027_available_scan_masks[] = {
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MAX1X27_SCAN_MASKS(0),
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MAX1X27_SCAN_MASKS(1),
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0x00000000,
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};
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static const unsigned long max1029_available_scan_masks[] = {
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MAX1X29_SCAN_MASKS(0),
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MAX1X29_SCAN_MASKS(1),
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0x00000000,
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};
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static const unsigned long max1031_available_scan_masks[] = {
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MAX1X31_SCAN_MASKS(0),
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MAX1X31_SCAN_MASKS(1),
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0x00000000,
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};
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struct max1027_chip_info {
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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const unsigned long *available_scan_masks;
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};
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static const struct max1027_chip_info max1027_chip_info_tbl[] = {
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[max1027] = {
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.channels = max1027_channels,
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.num_channels = ARRAY_SIZE(max1027_channels),
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.available_scan_masks = max1027_available_scan_masks,
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},
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[max1029] = {
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.channels = max1029_channels,
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.num_channels = ARRAY_SIZE(max1029_channels),
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.available_scan_masks = max1029_available_scan_masks,
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},
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[max1031] = {
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.channels = max1031_channels,
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.num_channels = ARRAY_SIZE(max1031_channels),
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.available_scan_masks = max1031_available_scan_masks,
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},
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[max1227] = {
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.channels = max1227_channels,
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.num_channels = ARRAY_SIZE(max1227_channels),
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.available_scan_masks = max1027_available_scan_masks,
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},
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[max1229] = {
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.channels = max1229_channels,
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.num_channels = ARRAY_SIZE(max1229_channels),
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.available_scan_masks = max1029_available_scan_masks,
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},
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[max1231] = {
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.channels = max1231_channels,
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.num_channels = ARRAY_SIZE(max1231_channels),
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.available_scan_masks = max1031_available_scan_masks,
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},
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};
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struct max1027_state {
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const struct max1027_chip_info *info;
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struct spi_device *spi;
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struct iio_trigger *trig;
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__be16 *buffer;
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struct mutex lock;
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struct completion complete;
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u8 reg __aligned(IIO_DMA_MINALIGN);
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};
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static int max1027_wait_eoc(struct iio_dev *indio_dev)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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unsigned int conversion_time = MAX1027_CONVERSION_UDELAY;
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int ret;
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if (st->spi->irq) {
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ret = wait_for_completion_timeout(&st->complete,
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msecs_to_jiffies(1000));
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reinit_completion(&st->complete);
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if (!ret)
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return -ETIMEDOUT;
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} else {
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if (indio_dev->active_scan_mask)
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conversion_time *= hweight32(*indio_dev->active_scan_mask);
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usleep_range(conversion_time, conversion_time * 2);
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}
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return 0;
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}
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/* Scan from chan 0 to the highest requested channel. Include temperature on demand. */
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static int max1027_configure_chans_and_start(struct iio_dev *indio_dev)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N;
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st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2);
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if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP)
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st->reg |= MAX1027_TEMP;
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return spi_write(st->spi, &st->reg, 1);
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}
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static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2;
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/*
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* Start acquisition on:
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* MODE0: external hardware trigger wired to the cnvst input pin
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* MODE2: conversion register write
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*/
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if (enable)
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st->reg |= MAX1027_CKS_MODE0;
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else
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st->reg |= MAX1027_CKS_MODE2;
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return spi_write(st->spi, &st->reg, 1);
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}
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static int max1027_read_single_value(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val)
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{
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int ret;
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struct max1027_state *st = iio_priv(indio_dev);
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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/* Configure conversion register with the requested chan */
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st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
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MAX1027_NOSCAN;
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if (chan->type == IIO_TEMP)
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st->reg |= MAX1027_TEMP;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0) {
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dev_err(&indio_dev->dev,
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"Failed to configure conversion register\n");
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goto release;
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}
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/*
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* For an unknown reason, when we use the mode "10" (write
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* conversion register), the interrupt doesn't occur every time.
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* So we just wait the maximum conversion time and deliver the value.
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*/
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ret = max1027_wait_eoc(indio_dev);
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if (ret)
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goto release;
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/* Read result */
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ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
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release:
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iio_device_release_direct_mode(indio_dev);
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if (ret < 0)
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return ret;
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*val = be16_to_cpu(st->buffer[0]);
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return IIO_VAL_INT;
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}
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static int max1027_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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int ret = 0;
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struct max1027_state *st = iio_priv(indio_dev);
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mutex_lock(&st->lock);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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ret = max1027_read_single_value(indio_dev, chan, val);
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break;
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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case IIO_TEMP:
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*val = 1;
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*val2 = 8;
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ret = IIO_VAL_FRACTIONAL;
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break;
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case IIO_VOLTAGE:
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*val = 2500;
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*val2 = chan->scan_type.realbits;
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ret = IIO_VAL_FRACTIONAL_LOG2;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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mutex_unlock(&st->lock);
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return ret;
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}
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static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
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unsigned int reg, unsigned int writeval,
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unsigned int *readval)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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u8 *val = (u8 *)st->buffer;
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if (readval) {
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int ret = spi_read(st->spi, val, 2);
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*readval = be16_to_cpu(st->buffer[0]);
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return ret;
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}
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*val = (u8)writeval;
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return spi_write(st->spi, val, 1);
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}
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static int max1027_set_cnvst_trigger_state(struct iio_trigger *trig, bool state)
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{
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struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
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int ret;
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/*
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* In order to disable the convst trigger, start acquisition on
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* conversion register write, which basically disables triggering
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* conversions upon cnvst changes and thus has the effect of disabling
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* the external hardware trigger.
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*/
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ret = max1027_enable_trigger(indio_dev, state);
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if (ret)
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return ret;
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if (state) {
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ret = max1027_configure_chans_and_start(indio_dev);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int max1027_read_scan(struct iio_dev *indio_dev)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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unsigned int scanned_chans;
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int ret;
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scanned_chans = fls(*indio_dev->active_scan_mask) - 1;
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if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP)
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scanned_chans++;
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/* fill buffer with all channel */
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ret = spi_read(st->spi, st->buffer, scanned_chans * 2);
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if (ret < 0)
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return ret;
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iio_push_to_buffers(indio_dev, st->buffer);
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return 0;
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}
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static irqreturn_t max1027_handler(int irq, void *private)
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{
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struct iio_dev *indio_dev = private;
|
|
struct max1027_state *st = iio_priv(indio_dev);
|
|
|
|
/*
|
|
* If buffers are disabled (raw read) or when using external triggers,
|
|
* we just need to unlock the waiters which will then handle the data.
|
|
*
|
|
* When using the internal trigger, we must hand-off the choice of the
|
|
* handler to the core which will then lookup through the interrupt tree
|
|
* for the right handler registered with iio_triggered_buffer_setup()
|
|
* to execute, as this trigger might very well be used in conjunction
|
|
* with another device. The core will then call the relevant handler to
|
|
* perform the data processing step.
|
|
*/
|
|
if (!iio_buffer_enabled(indio_dev))
|
|
complete(&st->complete);
|
|
else
|
|
iio_trigger_poll(indio_dev->trig);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t max1027_trigger_handler(int irq, void *private)
|
|
{
|
|
struct iio_poll_func *pf = private;
|
|
struct iio_dev *indio_dev = pf->indio_dev;
|
|
int ret;
|
|
|
|
if (!iio_trigger_using_own(indio_dev)) {
|
|
ret = max1027_configure_chans_and_start(indio_dev);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* This is a threaded handler, it is fine to wait for an IRQ */
|
|
ret = max1027_wait_eoc(indio_dev);
|
|
if (ret)
|
|
goto out;
|
|
}
|
|
|
|
ret = max1027_read_scan(indio_dev);
|
|
out:
|
|
if (ret)
|
|
dev_err(&indio_dev->dev,
|
|
"Cannot read scanned values (%d)\n", ret);
|
|
|
|
iio_trigger_notify_done(indio_dev->trig);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct iio_trigger_ops max1027_trigger_ops = {
|
|
.validate_device = &iio_trigger_validate_own_device,
|
|
.set_trigger_state = &max1027_set_cnvst_trigger_state,
|
|
};
|
|
|
|
static const struct iio_info max1027_info = {
|
|
.read_raw = &max1027_read_raw,
|
|
.debugfs_reg_access = &max1027_debugfs_reg_access,
|
|
};
|
|
|
|
static int max1027_probe(struct spi_device *spi)
|
|
{
|
|
int ret;
|
|
struct iio_dev *indio_dev;
|
|
struct max1027_state *st;
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (!indio_dev) {
|
|
pr_err("Can't allocate iio device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
st = iio_priv(indio_dev);
|
|
st->spi = spi;
|
|
st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
|
|
|
|
mutex_init(&st->lock);
|
|
init_completion(&st->complete);
|
|
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
|
indio_dev->info = &max1027_info;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = st->info->channels;
|
|
indio_dev->num_channels = st->info->num_channels;
|
|
indio_dev->available_scan_masks = st->info->available_scan_masks;
|
|
|
|
st->buffer = devm_kmalloc_array(&indio_dev->dev,
|
|
indio_dev->num_channels, 2,
|
|
GFP_KERNEL);
|
|
if (!st->buffer)
|
|
return -ENOMEM;
|
|
|
|
/* Enable triggered buffers */
|
|
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
|
|
&iio_pollfunc_store_time,
|
|
&max1027_trigger_handler,
|
|
NULL);
|
|
if (ret < 0) {
|
|
dev_err(&indio_dev->dev, "Failed to setup buffer\n");
|
|
return ret;
|
|
}
|
|
|
|
/* If there is an EOC interrupt, register the cnvst hardware trigger */
|
|
if (spi->irq) {
|
|
st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
|
|
indio_dev->name);
|
|
if (!st->trig) {
|
|
ret = -ENOMEM;
|
|
dev_err(&indio_dev->dev,
|
|
"Failed to allocate iio trigger\n");
|
|
return ret;
|
|
}
|
|
|
|
st->trig->ops = &max1027_trigger_ops;
|
|
iio_trigger_set_drvdata(st->trig, indio_dev);
|
|
ret = devm_iio_trigger_register(&indio_dev->dev,
|
|
st->trig);
|
|
if (ret < 0) {
|
|
dev_err(&indio_dev->dev,
|
|
"Failed to register iio trigger\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler,
|
|
IRQF_TRIGGER_FALLING,
|
|
spi->dev.driver->name, indio_dev);
|
|
if (ret < 0) {
|
|
dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Internal reset */
|
|
st->reg = MAX1027_RST_REG;
|
|
ret = spi_write(st->spi, &st->reg, 1);
|
|
if (ret < 0) {
|
|
dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Disable averaging */
|
|
st->reg = MAX1027_AVG_REG;
|
|
ret = spi_write(st->spi, &st->reg, 1);
|
|
if (ret < 0) {
|
|
dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Assume conversion on register write for now */
|
|
ret = max1027_enable_trigger(indio_dev, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_iio_device_register(&spi->dev, indio_dev);
|
|
}
|
|
|
|
static struct spi_driver max1027_driver = {
|
|
.driver = {
|
|
.name = "max1027",
|
|
.of_match_table = max1027_adc_dt_ids,
|
|
},
|
|
.probe = max1027_probe,
|
|
.id_table = max1027_id,
|
|
};
|
|
module_spi_driver(max1027_driver);
|
|
|
|
MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
|
|
MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
|
|
MODULE_LICENSE("GPL v2");
|