8de3e97f3d
When the Tx FIFO is empty and the last command has no STOP bit set, the master holds SCL low. If I2C_DYNAMIC_TAR_UPDATE is not set, BIT(13) MST_ON_HOLD of IC_RAW_INTR_STAT is not enabled, causing the __i2c_dw_disable() timeout. This is quite similar to commit |
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.. | ||
algos | ||
busses | ||
muxes | ||
i2c-atr.c | ||
i2c-boardinfo.c | ||
i2c-core-acpi.c | ||
i2c-core-base.c | ||
i2c-core-of.c | ||
i2c-core-slave.c | ||
i2c-core-smbus.c | ||
i2c-core.h | ||
i2c-dev.c | ||
i2c-mux.c | ||
i2c-slave-eeprom.c | ||
i2c-slave-testunit.c | ||
i2c-smbus.c | ||
i2c-stub.c | ||
Kconfig | ||
Makefile |