be37542afb
AM62Ax has 3 SPI channels where each channel has 4x TX and 4x RX
threads. Also fix the thread numbers to match what the firmware expects
according to the PSI-L device description.
Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62ax/psil_cfg.html [1]
Fixes: aac6db7e24 ("dmaengine: ti: k3-psil-am62a: Add AM62Ax PSIL and PDMA data")
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20231123-psil_fix-v1-1-6604d80819be@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
197 lines
4.6 KiB
C
197 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.mapped_channel_id = -1, \
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.default_flow_id = -1, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.mapped_channel_id = -1, \
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.default_flow_id = -1, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = flow_base, \
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}, \
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}
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#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = default_flow, \
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.notdpkt = tx, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_CSI2RX(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep am62a_src_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
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PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
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PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
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PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
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/* PDMA_MAIN0 - SPI0-2 */
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PSIL_PDMA_XY_PKT(0x4300),
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PSIL_PDMA_XY_PKT(0x4301),
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PSIL_PDMA_XY_PKT(0x4302),
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PSIL_PDMA_XY_PKT(0x4303),
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PSIL_PDMA_XY_PKT(0x4304),
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PSIL_PDMA_XY_PKT(0x4305),
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PSIL_PDMA_XY_PKT(0x4306),
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PSIL_PDMA_XY_PKT(0x4307),
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PSIL_PDMA_XY_PKT(0x4308),
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PSIL_PDMA_XY_PKT(0x4309),
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PSIL_PDMA_XY_PKT(0x430a),
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PSIL_PDMA_XY_PKT(0x430b),
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/* PDMA_MAIN1 - UART0-6 */
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PSIL_PDMA_XY_PKT(0x4400),
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PSIL_PDMA_XY_PKT(0x4401),
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PSIL_PDMA_XY_PKT(0x4402),
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PSIL_PDMA_XY_PKT(0x4403),
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PSIL_PDMA_XY_PKT(0x4404),
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PSIL_PDMA_XY_PKT(0x4405),
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PSIL_PDMA_XY_PKT(0x4406),
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/* PDMA_MAIN2 - MCASP0-2 */
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PSIL_PDMA_MCASP(0x4500),
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PSIL_PDMA_MCASP(0x4501),
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PSIL_PDMA_MCASP(0x4502),
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/* CPSW3G */
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PSIL_ETHERNET(0x4600, 19, 19, 16),
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/* CSI2RX */
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PSIL_CSI2RX(0x5000),
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PSIL_CSI2RX(0x5001),
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PSIL_CSI2RX(0x5002),
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PSIL_CSI2RX(0x5003),
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PSIL_CSI2RX(0x5004),
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PSIL_CSI2RX(0x5005),
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PSIL_CSI2RX(0x5006),
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PSIL_CSI2RX(0x5007),
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PSIL_CSI2RX(0x5008),
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PSIL_CSI2RX(0x5009),
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PSIL_CSI2RX(0x500a),
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PSIL_CSI2RX(0x500b),
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PSIL_CSI2RX(0x500c),
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PSIL_CSI2RX(0x500d),
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PSIL_CSI2RX(0x500e),
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PSIL_CSI2RX(0x500f),
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PSIL_CSI2RX(0x5010),
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PSIL_CSI2RX(0x5011),
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PSIL_CSI2RX(0x5012),
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PSIL_CSI2RX(0x5013),
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PSIL_CSI2RX(0x5014),
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PSIL_CSI2RX(0x5015),
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PSIL_CSI2RX(0x5016),
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PSIL_CSI2RX(0x5017),
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PSIL_CSI2RX(0x5018),
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PSIL_CSI2RX(0x5019),
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PSIL_CSI2RX(0x501a),
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PSIL_CSI2RX(0x501b),
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PSIL_CSI2RX(0x501c),
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PSIL_CSI2RX(0x501d),
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PSIL_CSI2RX(0x501e),
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PSIL_CSI2RX(0x501f),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep am62a_dst_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
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PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
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/* PDMA_MAIN0 - SPI0-2 */
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PSIL_PDMA_XY_PKT(0xc300),
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PSIL_PDMA_XY_PKT(0xc301),
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PSIL_PDMA_XY_PKT(0xc302),
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PSIL_PDMA_XY_PKT(0xc303),
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PSIL_PDMA_XY_PKT(0xc304),
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PSIL_PDMA_XY_PKT(0xc305),
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PSIL_PDMA_XY_PKT(0xc306),
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PSIL_PDMA_XY_PKT(0xc307),
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PSIL_PDMA_XY_PKT(0xc308),
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PSIL_PDMA_XY_PKT(0xc309),
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PSIL_PDMA_XY_PKT(0xc30a),
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PSIL_PDMA_XY_PKT(0xc30b),
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/* PDMA_MAIN1 - UART0-6 */
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PSIL_PDMA_XY_PKT(0xc400),
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PSIL_PDMA_XY_PKT(0xc401),
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PSIL_PDMA_XY_PKT(0xc402),
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PSIL_PDMA_XY_PKT(0xc403),
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PSIL_PDMA_XY_PKT(0xc404),
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PSIL_PDMA_XY_PKT(0xc405),
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PSIL_PDMA_XY_PKT(0xc406),
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/* PDMA_MAIN2 - MCASP0-2 */
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PSIL_PDMA_MCASP(0xc500),
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PSIL_PDMA_MCASP(0xc501),
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PSIL_PDMA_MCASP(0xc502),
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/* CPSW3G */
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PSIL_ETHERNET(0xc600, 19, 19, 8),
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PSIL_ETHERNET(0xc601, 20, 27, 8),
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PSIL_ETHERNET(0xc602, 21, 35, 8),
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PSIL_ETHERNET(0xc603, 22, 43, 8),
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PSIL_ETHERNET(0xc604, 23, 51, 8),
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PSIL_ETHERNET(0xc605, 24, 59, 8),
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PSIL_ETHERNET(0xc606, 25, 67, 8),
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PSIL_ETHERNET(0xc607, 26, 75, 8),
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};
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struct psil_ep_map am62a_ep_map = {
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.name = "am62a",
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.src = am62a_src_ep_map,
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.src_count = ARRAY_SIZE(am62a_src_ep_map),
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.dst = am62a_dst_ep_map,
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.dst_count = ARRAY_SIZE(am62a_dst_ep_map),
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};
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