466da3d2d9
Address the sparse warnings " sparse warnings: (new ones prefixed by >>) >> drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse: Using plain integer as NULL pointer " Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406220536.JnAncjqz-lkp@intel.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240624024351.488492-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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*/
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "../clk-fractional-divider.h"
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#include "clk.h"
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#define PCG_PR_MASK BIT(31)
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#define PCG_PCS_SHIFT 24
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#define PCG_PCS_MASK 0x7
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#define PCG_CGC_SHIFT 30
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#define PCG_FRAC_SHIFT 3
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#define PCG_FRAC_WIDTH 1
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#define PCG_PCD_SHIFT 0
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#define PCG_PCD_WIDTH 3
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#define SW_RST BIT(28)
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static int pcc_gate_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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unsigned long flags;
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u32 val;
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int ret;
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ret = clk_gate_ops.enable(hw);
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if (ret)
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return ret;
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spin_lock_irqsave(gate->lock, flags);
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/*
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* release the sw reset for peripherals associated with
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* with this pcc clock.
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*/
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val = readl(gate->reg);
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val |= SW_RST;
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writel(val, gate->reg);
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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static void pcc_gate_disable(struct clk_hw *hw)
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{
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clk_gate_ops.disable(hw);
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}
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static int pcc_gate_is_enabled(struct clk_hw *hw)
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{
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return clk_gate_ops.is_enabled(hw);
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}
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static const struct clk_ops pcc_gate_ops = {
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.enable = pcc_gate_enable,
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.disable = pcc_gate_disable,
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.is_enabled = pcc_gate_is_enabled,
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};
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static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
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const char * const *parent_names,
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int num_parents, bool mux_present,
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bool rate_present, bool gate_present,
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void __iomem *reg, bool has_swrst)
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{
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struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
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struct clk_fractional_divider *fd = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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struct clk_hw *hw;
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u32 val;
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val = readl(reg);
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if (!(val & PCG_PR_MASK)) {
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pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
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return NULL;
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}
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if (mux_present) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux_hw = &mux->hw;
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mux->reg = reg;
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mux->shift = PCG_PCS_SHIFT;
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mux->mask = PCG_PCS_MASK;
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if (has_swrst)
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mux->lock = &imx_ccm_lock;
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}
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if (rate_present) {
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd) {
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kfree(mux);
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return ERR_PTR(-ENOMEM);
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}
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fd_hw = &fd->hw;
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fd->reg = reg;
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fd->mshift = PCG_FRAC_SHIFT;
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fd->mwidth = PCG_FRAC_WIDTH;
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fd->nshift = PCG_PCD_SHIFT;
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fd->nwidth = PCG_PCD_WIDTH;
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fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
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if (has_swrst)
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fd->lock = &imx_ccm_lock;
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}
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if (gate_present) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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kfree(mux);
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kfree(fd);
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return ERR_PTR(-ENOMEM);
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}
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = PCG_CGC_SHIFT;
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if (has_swrst)
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gate->lock = &imx_ccm_lock;
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/*
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* make sure clock is gated during clock tree initialization,
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* the HW ONLY allow clock parent/rate changed with clock gated,
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* during clock tree initialization, clocks could be enabled
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* by bootloader, so the HW status will mismatch with clock tree
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* prepare count, then clock core driver will allow parent/rate
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* change since the prepare count is zero, but HW actually
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* prevent the parent/rate change due to the clock is enabled.
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*/
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val = readl_relaxed(reg);
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val &= ~(1 << PCG_CGC_SHIFT);
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writel_relaxed(val, reg);
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}
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ops, fd_hw,
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&clk_fractional_divider_ops, gate_hw,
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has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE |
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CLK_SET_PARENT_GATE | CLK_SET_RATE_NO_REPARENT);
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if (IS_ERR(hw)) {
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kfree(mux);
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kfree(fd);
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kfree(gate);
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}
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return hw;
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}
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struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names,
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int num_parents, bool mux_present, bool rate_present,
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bool gate_present, void __iomem *reg)
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{
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return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
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gate_present, reg, false);
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}
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struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names,
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int num_parents, bool mux_present, bool rate_present,
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bool gate_present, void __iomem *reg, bool has_swrst)
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{
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return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
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gate_present, reg, has_swrst);
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}
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EXPORT_SYMBOL_GPL(imx8ulp_clk_hw_composite);
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