1c450ffef5
Advertise AVX10.1 related CPUIDs, i.e. report AVX10 support bit via
CPUID.(EAX=07H, ECX=01H):EDX[bit 19] and new CPUID leaf 0x24H so that
guest OS and applications can query the AVX10.1 CPUIDs directly. Intel
AVX10 represents the first major new vector ISA since the introduction of
Intel AVX512, which will establish a common, converged vector instruction
set across all Intel architectures[1].
AVX10.1 is an early version of AVX10, that enumerates the Intel AVX512
instruction set at 128, 256, and 512 bits which is enabled on
Granite Rapids. I.e., AVX10.1 is only a new CPUID enumeration with no
new functionality. New features, e.g. Embedded Rounding and Suppress
All Exceptions (SAE) will be introduced in AVX10.2.
Advertising AVX10.1 is safe because there is nothing to enable for AVX10.1,
i.e. it's purely a new way to enumerate support, thus there will never be
anything for the kernel to enable. Note just the CPUID checking is changed
when using AVX512 related instructions, e.g. if using one AVX512
instruction needs to check (AVX512 AND AVX512DQ), it can check
((AVX512 AND AVX512DQ) OR AVX10.1) after checking XCR0[7:5].
The versions of AVX10 are expected to be inclusive, e.g. version N+1 is
a superset of version N. Per the spec, the version can never be 0, just
advertise AVX10.1 if it's supported in hardware. Moreover, advertising
AVX10_{128,256,512} needs to land in the same commit as advertising basic
AVX10.1 support, otherwise KVM would advertise an impossible CPU model.
E.g. a CPU with AVX512 but not AVX10.1/512 is impossible per the SDM.
As more and more AVX related CPUIDs are added (it would have resulted in
around 40-50 CPUID flags when developing AVX10), the versioning approach
is introduced. But incrementing version numbers are bad for virtualization.
E.g. if AVX10.2 has a feature that shouldn't be enumerated to guests for
whatever reason, then KVM can't enumerate any "later" features either,
because the only way to hide the problematic AVX10.2 feature is to set the
version to AVX10.1 or lower[2]. But most AVX features are just passed
through and don't have virtualization controls, so AVX10 should not be
problematic in practice, so long as Intel honors their promise that future
versions will be supersets of past versions.
[1] https://cdrdv2.intel.com/v1/dl/getContent/784267
[2] https://lore.kernel.org/all/Zkz5Ak0PQlAN8DxK@google.com/
Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Link: https://lore.kernel.org/r/20240819062327.3269720-1-tao1.su@linux.intel.com
[sean: minor changelog tweaks]
Signed-off-by: Sean Christopherson <seanjc@google.com>
247 lines
8.2 KiB
C
247 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_KVM_REVERSE_CPUID_H
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#define ARCH_X86_KVM_REVERSE_CPUID_H
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#include <uapi/asm/kvm.h>
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#include <asm/cpufeature.h>
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#include <asm/cpufeatures.h>
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/*
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* Hardware-defined CPUID leafs that are either scattered by the kernel or are
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* unknown to the kernel, but need to be directly used by KVM. Note, these
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* word values conflict with the kernel's "bug" caps, but KVM doesn't use those.
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*/
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enum kvm_only_cpuid_leafs {
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CPUID_12_EAX = NCAPINTS,
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CPUID_7_1_EDX,
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CPUID_8000_0007_EDX,
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CPUID_8000_0022_EAX,
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CPUID_7_2_EDX,
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CPUID_24_0_EBX,
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NR_KVM_CPU_CAPS,
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NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
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};
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/*
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* Define a KVM-only feature flag.
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*
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* For features that are scattered by cpufeatures.h, __feature_translate() also
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* needs to be updated to translate the kernel-defined feature into the
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* KVM-defined feature.
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*
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* For features that are 100% KVM-only, i.e. not defined by cpufeatures.h,
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* forego the intermediate KVM_X86_FEATURE and directly define X86_FEATURE_* so
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* that X86_FEATURE_* can be used in KVM. No __feature_translate() handling is
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* needed in this case.
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*/
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#define KVM_X86_FEATURE(w, f) ((w)*32 + (f))
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/* Intel-defined SGX sub-features, CPUID level 0x12 (EAX). */
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#define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0)
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#define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1)
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#define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11)
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/* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
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#define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
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#define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
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#define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
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#define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
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#define X86_FEATURE_AVX10 KVM_X86_FEATURE(CPUID_7_1_EDX, 19)
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/* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */
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#define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0)
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#define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1)
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#define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2)
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#define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3)
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#define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
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#define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
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/* Intel-defined sub-features, CPUID level 0x00000024:0 (EBX) */
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#define X86_FEATURE_AVX10_128 KVM_X86_FEATURE(CPUID_24_0_EBX, 16)
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#define X86_FEATURE_AVX10_256 KVM_X86_FEATURE(CPUID_24_0_EBX, 17)
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#define X86_FEATURE_AVX10_512 KVM_X86_FEATURE(CPUID_24_0_EBX, 18)
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/* CPUID level 0x80000007 (EDX). */
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#define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8)
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/* CPUID level 0x80000022 (EAX) */
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#define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0)
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struct cpuid_reg {
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u32 function;
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u32 index;
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int reg;
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};
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static const struct cpuid_reg reverse_cpuid[] = {
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[CPUID_1_EDX] = { 1, 0, CPUID_EDX},
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[CPUID_8000_0001_EDX] = {0x80000001, 0, CPUID_EDX},
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[CPUID_8086_0001_EDX] = {0x80860001, 0, CPUID_EDX},
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[CPUID_1_ECX] = { 1, 0, CPUID_ECX},
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[CPUID_C000_0001_EDX] = {0xc0000001, 0, CPUID_EDX},
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[CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX},
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[CPUID_7_0_EBX] = { 7, 0, CPUID_EBX},
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[CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX},
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[CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX},
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[CPUID_6_EAX] = { 6, 0, CPUID_EAX},
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[CPUID_8000_000A_EDX] = {0x8000000a, 0, CPUID_EDX},
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[CPUID_7_ECX] = { 7, 0, CPUID_ECX},
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[CPUID_8000_0007_EBX] = {0x80000007, 0, CPUID_EBX},
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[CPUID_7_EDX] = { 7, 0, CPUID_EDX},
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[CPUID_7_1_EAX] = { 7, 1, CPUID_EAX},
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[CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
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[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
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[CPUID_7_1_EDX] = { 7, 1, CPUID_EDX},
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[CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX},
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[CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
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[CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX},
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[CPUID_7_2_EDX] = { 7, 2, CPUID_EDX},
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[CPUID_24_0_EBX] = { 0x24, 0, CPUID_EBX},
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};
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/*
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* Reverse CPUID and its derivatives can only be used for hardware-defined
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* feature words, i.e. words whose bits directly correspond to a CPUID leaf.
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* Retrieving a feature bit or masking guest CPUID from a Linux-defined word
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* is nonsensical as the bit number/mask is an arbitrary software-defined value
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* and can't be used by KVM to query/control guest capabilities. And obviously
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* the leaf being queried must have an entry in the lookup table.
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*/
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static __always_inline void reverse_cpuid_check(unsigned int x86_leaf)
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{
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BUILD_BUG_ON(NR_CPUID_WORDS != NCAPINTS);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_1);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_2);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_3);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_4);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_5);
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BUILD_BUG_ON(x86_leaf >= ARRAY_SIZE(reverse_cpuid));
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BUILD_BUG_ON(reverse_cpuid[x86_leaf].function == 0);
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}
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/*
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* Translate feature bits that are scattered in the kernel's cpufeatures word
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* into KVM feature words that align with hardware's definitions.
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*/
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static __always_inline u32 __feature_translate(int x86_feature)
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{
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#define KVM_X86_TRANSLATE_FEATURE(f) \
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case X86_FEATURE_##f: return KVM_X86_FEATURE_##f
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switch (x86_feature) {
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KVM_X86_TRANSLATE_FEATURE(SGX1);
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KVM_X86_TRANSLATE_FEATURE(SGX2);
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KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA);
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KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC);
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KVM_X86_TRANSLATE_FEATURE(PERFMON_V2);
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KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL);
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KVM_X86_TRANSLATE_FEATURE(BHI_CTRL);
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default:
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return x86_feature;
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}
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}
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static __always_inline u32 __feature_leaf(int x86_feature)
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{
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return __feature_translate(x86_feature) / 32;
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}
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/*
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* Retrieve the bit mask from an X86_FEATURE_* definition. Features contain
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* the hardware defined bit number (stored in bits 4:0) and a software defined
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* "word" (stored in bits 31:5). The word is used to index into arrays of
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* bit masks that hold the per-cpu feature capabilities, e.g. this_cpu_has().
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*/
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static __always_inline u32 __feature_bit(int x86_feature)
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{
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x86_feature = __feature_translate(x86_feature);
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reverse_cpuid_check(x86_feature / 32);
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return 1 << (x86_feature & 31);
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}
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#define feature_bit(name) __feature_bit(X86_FEATURE_##name)
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static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned int x86_feature)
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{
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unsigned int x86_leaf = __feature_leaf(x86_feature);
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reverse_cpuid_check(x86_leaf);
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return reverse_cpuid[x86_leaf];
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}
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static __always_inline u32 *__cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
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u32 reg)
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{
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switch (reg) {
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case CPUID_EAX:
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return &entry->eax;
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case CPUID_EBX:
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return &entry->ebx;
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case CPUID_ECX:
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return &entry->ecx;
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case CPUID_EDX:
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return &entry->edx;
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default:
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BUILD_BUG();
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return NULL;
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}
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}
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static __always_inline u32 *cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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const struct cpuid_reg cpuid = x86_feature_cpuid(x86_feature);
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return __cpuid_entry_get_reg(entry, cpuid.reg);
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}
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static __always_inline u32 cpuid_entry_get(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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return *reg & __feature_bit(x86_feature);
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}
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static __always_inline bool cpuid_entry_has(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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return cpuid_entry_get(entry, x86_feature);
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}
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static __always_inline void cpuid_entry_clear(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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*reg &= ~__feature_bit(x86_feature);
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}
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static __always_inline void cpuid_entry_set(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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*reg |= __feature_bit(x86_feature);
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}
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static __always_inline void cpuid_entry_change(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature,
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bool set)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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/*
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* Open coded instead of using cpuid_entry_{clear,set}() to coerce the
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* compiler into using CMOV instead of Jcc when possible.
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*/
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if (set)
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*reg |= __feature_bit(x86_feature);
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else
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*reg &= ~__feature_bit(x86_feature);
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}
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#endif /* ARCH_X86_KVM_REVERSE_CPUID_H */
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