035fc90a9d
Now that the core code does not use this monstrosity anymore, it's time to put it to rest. The only real purpose was to read the APIC ID on UV and VSMP systems for the actual evaluation. That's what the core code does now. For doing the actual shift operation there is truly no APIC callback required. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mhklinux@outlook.com> Tested-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Wang Wendy <wendy.wang@intel.com> Tested-by: K Prateek Nayak <kprateek.nayak@amd.com> Link: https://lore.kernel.org/r/20240212153625.516536121@linutronix.de
141 lines
3.0 KiB
C
141 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* vSMPowered(tm) systems specific initialization
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* Copyright (C) 2005 ScaleMP Inc.
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*
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* Ravikiran Thirumalai <kiran@scalemp.com>,
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* Shai Fultheim <shai@scalemp.com>
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* Paravirt ops integration: Glauber de Oliveira Costa <gcosta@redhat.com>,
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* Ravikiran Thirumalai <kiran@scalemp.com>
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*/
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#include <linux/init.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/apic.h>
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#include <asm/pci-direct.h>
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#include <asm/io.h>
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#include <asm/paravirt.h>
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#include <asm/setup.h>
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#define TOPOLOGY_REGISTER_OFFSET 0x10
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#ifdef CONFIG_PCI
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static void __init set_vsmp_ctl(void)
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{
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void __iomem *address;
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unsigned int cap, ctl, cfg;
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/* set vSMP magic bits to indicate vSMP capable kernel */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg, 8);
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cap = readl(address);
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ctl = readl(address + 4);
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printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n",
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cap, ctl);
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/* If possible, let the vSMP foundation route the interrupt optimally */
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#ifdef CONFIG_SMP
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if (cap & ctl & BIT(8)) {
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ctl &= ~BIT(8);
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#ifdef CONFIG_PROC_FS
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/* Don't let users change irq affinity via procfs */
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no_irq_affinity = 1;
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#endif
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}
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#endif
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writel(ctl, address + 4);
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ctl = readl(address + 4);
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pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
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early_iounmap(address, 8);
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}
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static int is_vsmp = -1;
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static void __init detect_vsmp_box(void)
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{
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is_vsmp = 0;
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if (!early_pci_allowed())
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return;
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/* Check if we are running on a ScaleMP vSMPowered box */
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if (read_pci_config(0, 0x1f, 0, PCI_VENDOR_ID) ==
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(PCI_VENDOR_ID_SCALEMP | (PCI_DEVICE_ID_SCALEMP_VSMP_CTL << 16)))
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is_vsmp = 1;
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}
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static int is_vsmp_box(void)
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{
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if (is_vsmp != -1)
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return is_vsmp;
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else {
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WARN_ON_ONCE(1);
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return 0;
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}
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}
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#else
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static void __init detect_vsmp_box(void)
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{
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}
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static int is_vsmp_box(void)
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{
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return 0;
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}
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static void __init set_vsmp_ctl(void)
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{
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}
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#endif
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static void __init vsmp_cap_cpus(void)
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{
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#if !defined(CONFIG_X86_VSMP) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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void __iomem *address;
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unsigned int cfg, topology, node_shift, maxcpus;
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/*
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* CONFIG_X86_VSMP is not configured, so limit the number CPUs to the
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* ones present in the first board, unless explicitly overridden by
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* setup_max_cpus
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*/
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if (setup_max_cpus != NR_CPUS)
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return;
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/* Read the vSMP Foundation topology register */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg + TOPOLOGY_REGISTER_OFFSET, 4);
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if (WARN_ON(!address))
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return;
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topology = readl(address);
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node_shift = (topology >> 16) & 0x7;
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if (!node_shift)
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/* The value 0 should be decoded as 8 */
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node_shift = 8;
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maxcpus = (topology & ((1 << node_shift) - 1)) + 1;
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pr_info("vSMP CTL: Capping CPUs to %d (CONFIG_X86_VSMP is unset)\n",
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maxcpus);
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setup_max_cpus = maxcpus;
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early_iounmap(address, 4);
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#endif
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}
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void __init vsmp_init(void)
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{
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detect_vsmp_box();
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if (!is_vsmp_box())
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return;
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vsmp_cap_cpus();
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set_vsmp_ctl();
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return;
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}
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