4cdb71b6ba
Commit ddb5cdbafa ("kbuild: generate KSYMTAB entries by modpost")
deprecated <asm/export.h>, which is now a wrapper of <linux/export.h>.
Replace #include <asm/export.h> with #include <linux/export.h>.
After all the <asm/export.h> lines are converted, <asm/export.h> and
<asm-generic/export.h> will be removed.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
137 lines
2.4 KiB
ArmAsm
137 lines
2.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* memscan.S: Optimized memscan for Sparc64.
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*
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1998 David S. Miller (davem@redhat.com)
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*/
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#include <linux/export.h>
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#define HI_MAGIC 0x8080808080808080
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#define LO_MAGIC 0x0101010101010101
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#define ASI_PL 0x88
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.text
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.align 32
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.globl __memscan_zero, __memscan_generic
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.type __memscan_zero,#function
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.type __memscan_generic,#function
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.globl memscan
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EXPORT_SYMBOL(__memscan_zero)
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EXPORT_SYMBOL(__memscan_generic)
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__memscan_zero:
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/* %o0 = bufp, %o1 = size */
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brlez,pn %o1, szzero
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andcc %o0, 7, %g0
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be,pt %icc, we_are_aligned
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sethi %hi(HI_MAGIC), %o4
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ldub [%o0], %o5
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1: subcc %o1, 1, %o1
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brz,pn %o5, 10f
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add %o0, 1, %o0
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be,pn %xcc, szzero
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andcc %o0, 7, %g0
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bne,a,pn %icc, 1b
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ldub [%o0], %o5
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we_are_aligned:
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ldxa [%o0] ASI_PL, %o5
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or %o4, %lo(HI_MAGIC), %o3
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sllx %o3, 32, %o4
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or %o4, %o3, %o3
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srlx %o3, 7, %o2
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msloop:
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sub %o1, 8, %o1
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add %o0, 8, %o0
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sub %o5, %o2, %o4
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xor %o4, %o5, %o4
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andcc %o4, %o3, %g3
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bne,pn %xcc, check_bytes
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srlx %o4, 32, %g3
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brgz,a,pt %o1, msloop
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ldxa [%o0] ASI_PL, %o5
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check_bytes:
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bne,a,pn %icc, 2f
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andcc %o5, 0xff, %g0
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add %o0, -5, %g2
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ba,pt %xcc, 3f
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srlx %o5, 32, %g7
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2: srlx %o5, 8, %g7
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be,pn %icc, 1f
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add %o0, -8, %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g3, %o3, %g0
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be,a,pn %icc, 2f
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mov %o0, %g2
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3: andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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andcc %g7, 0xff, %g0
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srlx %g7, 8, %g7
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be,pn %icc, 1f
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inc %g2
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2: brgz,a,pt %o1, msloop
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ldxa [%o0] ASI_PL, %o5
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inc %g2
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1: add %o0, %o1, %o0
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cmp %g2, %o0
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retl
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movle %xcc, %g2, %o0
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10: retl
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sub %o0, 1, %o0
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szzero: retl
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nop
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memscan:
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__memscan_generic:
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/* %o0 = addr, %o1 = c, %o2 = size */
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brz,pn %o2, 3f
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add %o0, %o2, %o3
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ldub [%o0], %o5
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sub %g0, %o2, %o4
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1:
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cmp %o5, %o1
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be,pn %icc, 2f
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addcc %o4, 1, %o4
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bne,a,pt %xcc, 1b
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ldub [%o3 + %o4], %o5
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retl
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/* The delay slot is the same as the next insn, this is just to make it look more awful */
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2:
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add %o3, %o4, %o0
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retl
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sub %o0, 1, %o0
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3:
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retl
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nop
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