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linux/arch/riscv/include/uapi/asm
Evan Green 1f5288874d
RISC-V: hwprobe: Add SCALAR to misaligned perf defines
In preparation for misaligned vector performance hwprobe keys, rename
the hwprobe key values associated with misaligned scalar accesses to
include the term SCALAR. Leave the old defines in place to maintain
source compatibility.

This change is intended to be a functional no-op.

Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240809214444.3257596-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-08-14 13:13:24 -07:00
..
auxvec.h
bitsperlong.h
bpf_perf_event.h
byteorder.h
elf.h
hwcap.h
hwprobe.h RISC-V: hwprobe: Add SCALAR to misaligned perf defines 2024-08-14 13:13:24 -07:00
Kbuild riscv: convert to generic syscall table 2024-07-10 14:23:38 +02:00
kvm.h Merge patch series "riscv: Apply Zawrs when available" 2024-07-12 08:55:29 -07:00
perf_regs.h
ptrace.h
setup.h
sigcontext.h
ucontext.h
unistd.h riscv: convert to generic syscall table 2024-07-10 14:23:38 +02:00