c150b809f7
* Support for various vector-accelerated crypto routines.
* Hibernation is now enabled for portable kernel builds.
* mmap_rnd_bits_max is larger on systems with larger VAs.
* Support for fast GUP.
* Support for membarrier-based instruction cache synchronization.
* Support for the Andes hart-level interrupt controller and PMU.
* Some cleanups around unaligned access speed probing and Kconfig
settings.
* Support for ACPI LPI and CPPC.
* Various cleanus related to barriers.
* A handful of fixes.
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Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for various vector-accelerated crypto routines
- Hibernation is now enabled for portable kernel builds
- mmap_rnd_bits_max is larger on systems with larger VAs
- Support for fast GUP
- Support for membarrier-based instruction cache synchronization
- Support for the Andes hart-level interrupt controller and PMU
- Some cleanups around unaligned access speed probing and Kconfig
settings
- Support for ACPI LPI and CPPC
- Various cleanus related to barriers
- A handful of fixes
* tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits)
riscv: Fix syscall wrapper for >word-size arguments
crypto: riscv - add vector crypto accelerated AES-CBC-CTS
crypto: riscv - parallelize AES-CBC decryption
riscv: Only flush the mm icache when setting an exec pte
riscv: Use kcalloc() instead of kzalloc()
riscv/barrier: Add missing space after ','
riscv/barrier: Consolidate fence definitions
riscv/barrier: Define RISCV_FULL_BARRIER
riscv/barrier: Define __{mb,rmb,wmb}
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
ACPI: RISC-V: Add CPPC driver
ACPI: Enable ACPI_PROCESSOR for RISC-V
ACPI: RISC-V: Add LPI driver
cpuidle: RISC-V: Move few functions to arch/riscv
riscv: Introduce set_compat_task() in asm/compat.h
riscv: Introduce is_compat_thread() into compat.h
riscv: add compile-time test into is_compat_task()
riscv: Replace direct thread flag check with is_compat_task()
riscv: Improve arch_get_mmap_end() macro
...
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_TLB_H
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#define _ASM_RISCV_TLB_H
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struct mmu_gather;
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static void tlb_flush(struct mmu_gather *tlb);
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#ifdef CONFIG_MMU
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#include <linux/swap.h>
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/*
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* While riscv platforms with riscv_ipi_for_rfence as true require an IPI to
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* perform TLB shootdown, some platforms with riscv_ipi_for_rfence as false use
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* SBI to perform TLB shootdown. To keep software pagetable walkers safe in this
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* case we switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the
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* comment below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
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* for more details.
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*/
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static inline void __tlb_remove_table(void *table)
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{
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free_page_and_swap_cache(table);
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}
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#endif /* CONFIG_MMU */
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#define tlb_flush tlb_flush
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#include <asm-generic/tlb.h>
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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#ifdef CONFIG_MMU
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if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables)
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flush_tlb_mm(tlb->mm);
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else
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flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end,
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tlb_get_unmap_size(tlb));
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#endif
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}
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#endif /* _ASM_RISCV_TLB_H */
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