9a7e8ec0d4
For RISC-V, when tracing with tracepoint events, the IP and status are set to 0, preventing the perf code parsing the callchain and resolving the symbols correctly. ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' @: { <STACKID4294967282> }: 1 The fix is to implement perf_arch_fetch_caller_regs for riscv, which fills several necessary registers used for callchain unwinding, including epc, sp, s0 and status. It's similar to commitb3eac0265b
("arm: perf: Fix callchain parse error with kernel tracepoint events") and commit5b09a094f2
("arm64: perf: Fix callchain parse error with kernel tracepoint events"). With this patch, callchain can be parsed correctly as: ./ply 'tracepoint:kmem/kmem_cache_alloc { @[stack]=count(); }' @: { __traceiter_kmem_cache_alloc+68 __traceiter_kmem_cache_alloc+68 kmem_cache_alloc+354 __sigqueue_alloc+94 __send_signal_locked+646 send_signal_locked+154 do_send_sig_info+84 __kill_pgrp_info+130 kill_pgrp+60 isig+150 n_tty_receive_signal_char+36 n_tty_receive_buf_standard+2214 n_tty_receive_buf_common+280 n_tty_receive_buf2+26 tty_ldisc_receive_buf+34 tty_port_default_receive_buf+62 flush_to_ldisc+158 process_one_work+458 worker_thread+138 kthread+178 riscv_cpufeature_patch_func+832 }: 1 Signed-off-by: Ism Hong <ism.hong@gmail.com> Link: https://lore.kernel.org/r/20230601095355.1168910-1-ism.hong@gmail.com Fixes:178e9fc47a
("perf: riscv: preliminary RISC-V support") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
21 lines
541 B
C
21 lines
541 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 SiFive
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* Copyright (C) 2018 Andes Technology Corporation
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*
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*/
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#ifndef _ASM_RISCV_PERF_EVENT_H
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#define _ASM_RISCV_PERF_EVENT_H
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#include <linux/perf_event.h>
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#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
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#define perf_arch_fetch_caller_regs(regs, __ip) { \
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(regs)->epc = (__ip); \
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(regs)->s0 = (unsigned long) __builtin_frame_address(0); \
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(regs)->sp = current_stack_pointer; \
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(regs)->status = SR_PP; \
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}
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#endif /* _ASM_RISCV_PERF_EVENT_H */
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