5aa09297a3
The csr_fun defines a count parameter which defines the total number
CSRs emulated in KVM starting from the base. This value should be
equal to total number of counters possible for trap/emulation (32).
Fixes: a9ac6c3752 ("RISC-V: KVM: Implement trap & emulate for hpmcounters")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240816-kvm_pmu_fixes-v1-2-cdfce386dd93@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
133 lines
4.5 KiB
C
133 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023 Rivos Inc
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*
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* Authors:
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* Atish Patra <atishp@rivosinc.com>
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*/
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#ifndef __KVM_VCPU_RISCV_PMU_H
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#define __KVM_VCPU_RISCV_PMU_H
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#include <linux/perf/riscv_pmu.h>
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#include <asm/kvm_vcpu_insn.h>
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#include <asm/sbi.h>
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#ifdef CONFIG_RISCV_PMU_SBI
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#define RISCV_KVM_MAX_FW_CTRS 32
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#define RISCV_KVM_MAX_HW_CTRS 32
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#define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_CTRS)
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static_assert(RISCV_KVM_MAX_COUNTERS <= 64);
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struct kvm_fw_event {
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/* Current value of the event */
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u64 value;
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/* Event monitoring status */
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bool started;
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};
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/* Per virtual pmu counter data */
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struct kvm_pmc {
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u8 idx;
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struct perf_event *perf_event;
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u64 counter_val;
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union sbi_pmu_ctr_info cinfo;
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/* Event monitoring status */
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bool started;
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/* Monitoring event ID */
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unsigned long event_idx;
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struct kvm_vcpu *vcpu;
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};
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/* PMU data structure per vcpu */
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struct kvm_pmu {
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struct kvm_pmc pmc[RISCV_KVM_MAX_COUNTERS];
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struct kvm_fw_event fw_event[RISCV_KVM_MAX_FW_CTRS];
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/* Number of the virtual firmware counters available */
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int num_fw_ctrs;
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/* Number of the virtual hardware counters available */
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int num_hw_ctrs;
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/* A flag to indicate that pmu initialization is done */
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bool init_done;
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/* Bit map of all the virtual counter used */
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DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS);
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/* Bit map of all the virtual counter overflown */
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DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS);
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/* The address of the counter snapshot area (guest physical address) */
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gpa_t snapshot_addr;
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/* The actual data of the snapshot */
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struct riscv_pmu_snapshot_data *sdata;
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};
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#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context)
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#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu_context))
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#if defined(CONFIG_32BIT)
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#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \
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{.base = CSR_CYCLEH, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm }, \
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{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },
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#else
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#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \
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{.base = CSR_CYCLE, .count = 32, .func = kvm_riscv_vcpu_pmu_read_hpm },
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#endif
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int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid);
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int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx,
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struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags, u64 ival,
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struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags,
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struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags,
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unsigned long eidx, u64 evtdata,
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struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
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struct kvm_vcpu_sbi_return *retdata);
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int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx,
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struct kvm_vcpu_sbi_return *retdata);
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void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned long saddr_low,
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unsigned long saddr_high, unsigned long flags,
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struct kvm_vcpu_sbi_return *retdata);
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void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu);
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#else
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struct kvm_pmu {
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};
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static inline int kvm_riscv_vcpu_pmu_read_legacy(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask)
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{
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if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) {
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*val = 0;
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return KVM_INSN_CONTINUE_NEXT_SEPC;
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} else {
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return KVM_INSN_ILLEGAL_TRAP;
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}
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}
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#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \
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{.base = CSR_CYCLE, .count = 3, .func = kvm_riscv_vcpu_pmu_read_legacy },
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static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {}
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static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid)
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{
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return 0;
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}
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static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {}
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static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {}
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#endif /* CONFIG_RISCV_PMU_SBI */
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#endif /* !__KVM_VCPU_RISCV_PMU_H */
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