dcb2743d1e
After commit f51f7a0fc2 ("riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC
for !dma_coherent"), for non-coherent platforms with less than 4GB
memory, we rely on users to pass "swiotlb=mmnn,force" kernel parameters
to enable DMA bouncing for unaligned kmalloc() buffers. Now let's go
further: If no bouncing needed for ZONE_DMA, let kernel automatically
allocate 1MB swiotlb buffer per 1GB of RAM for kmalloc() bouncing on
non-coherent platforms, so that no need to pass "swiotlb=mmnn,force"
any more.
The math of "1MB swiotlb buffer per 1GB of RAM for kmalloc() bouncing"
is taken from arm64. Users can still force smaller swiotlb buffer by
passing "swiotlb=mmnn".
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240325110036.1564-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
41 lines
897 B
C
41 lines
897 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CACHE_H
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#define _ASM_RISCV_CACHE_H
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#define ARCH_KMALLOC_MINALIGN (8)
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#endif
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/*
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* RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
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* the flat loader aligns it accordingly.
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*/
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#ifndef CONFIG_MMU
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#define ARCH_SLAB_MINALIGN 16
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#endif
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#ifndef __ASSEMBLY__
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extern int dma_cache_alignment;
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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#define dma_get_cache_alignment dma_get_cache_alignment
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static inline int dma_get_cache_alignment(void)
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{
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return dma_cache_alignment;
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_CACHE_H */
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