23c996fc2b
Instead of grouping all vendor extensions into the same riscv_isa_ext that standard instructions use, create a struct "riscv_isa_vendor_ext_data_list" that allows each vendor to maintain their vendor extensions independently of the standard extensions. xandespmu is currently the only vendor extension so that is the only extension that is affected by this change. An additional benefit of this is that the extensions of each vendor can be conditionally enabled. A config RISCV_ISA_VENDOR_EXT_ANDES has been added to allow for that. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> Tested-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Link: https://lore.kernel.org/r/20240719-support_vendor_extensions-v3-1-0af7587bbec0@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
76 lines
1.8 KiB
C
76 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Erratas to be applied for Andes CPU cores
|
|
*
|
|
* Copyright (C) 2023 Renesas Electronics Corporation.
|
|
*
|
|
* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
|
*/
|
|
|
|
#include <linux/memory.h>
|
|
#include <linux/module.h>
|
|
|
|
#include <asm/alternative.h>
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/errata_list.h>
|
|
#include <asm/patch.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/sbi.h>
|
|
#include <asm/vendorid_list.h>
|
|
#include <asm/vendor_extensions.h>
|
|
|
|
#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
|
|
#define ANDES_AX45MP_MIMPID 0x500UL
|
|
#define ANDES_SBI_EXT_ANDES 0x0900031E
|
|
|
|
#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
|
|
|
|
static long ax45mp_iocp_sw_workaround(void)
|
|
{
|
|
struct sbiret ret;
|
|
|
|
/*
|
|
* ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
|
|
* cache is controllable only then CMO will be applied to the platform.
|
|
*/
|
|
ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
|
|
0, 0, 0, 0, 0, 0);
|
|
|
|
return ret.error ? 0 : ret.value;
|
|
}
|
|
|
|
static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
|
|
{
|
|
static bool done;
|
|
|
|
if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
|
|
return;
|
|
|
|
if (done)
|
|
return;
|
|
|
|
done = true;
|
|
|
|
if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
|
|
return;
|
|
|
|
if (!ax45mp_iocp_sw_workaround())
|
|
return;
|
|
|
|
/* Set this just to make core cbo code happy */
|
|
riscv_cbom_block_size = 1;
|
|
riscv_noncoherent_supported();
|
|
}
|
|
|
|
void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
|
|
unsigned long archid, unsigned long impid,
|
|
unsigned int stage)
|
|
{
|
|
BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
|
|
|
|
if (stage == RISCV_ALTERNATIVES_BOOT)
|
|
errata_probe_iocp(stage, archid, impid);
|
|
|
|
/* we have nothing to patch here ATM so just return back */
|
|
}
|