8f6aca0e0f
On power9 and earlier platforms, the default event used for cyles and
instructions is PM_CYC (0x0001e) and PM_INST_CMPL (0x00002)
respectively. These events use two programmable PMCs and by default will
count irrespective of the run latch state (idle state). But since they
use programmable PMCs, these events can lead to multiplexing with other
events, because there are only 4 programmable PMCs. Hence in power10,
performance monitoring unit (PMU) driver uses performance monitor
counter 5 (PMC5) and performance monitor counter6 (PMC6) for counting
instructions and cycles.
Currently on power10, the event used for cycles is PM_RUN_CYC (0x600F4)
and instructions uses PM_RUN_INST_CMPL (0x500fa). But counting of these
events in idle state is controlled by the CC56RUN bit setting in Monitor
Mode Control Register0 (MMCR0). If the CC56RUN bit is zero, PMC5/6 will
not count when CTRL[RUN] (run latch) is zero. This could lead to missing
some counts if a thread is in idle state during system wide profiling.
To fix it, set the CC56RUN bit in MMCR0 for power10, which makes PMC5
and PMC6 count instructions and cycles regardless of the run latch
state. Since this change make PMC5/6 count as PM_INST_CMPL/PM_CYC,
rename the event code 0x600f4 as PM_CYC instead of PM_RUN_CYC and event
code 0x500fa as PM_INST_CMPL instead of PM_RUN_INST_CMPL. The changes
are only for PMC5/6 event codes and will not affect the behaviour of
PM_RUN_CYC/PM_RUN_INST_CMPL if progammed in other PMC's.
Fixes: a64e697cef ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.cm>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Tweak change log wording for style and consistency]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211007075121.28497-1-atrajeev@linux.vnet.ibm.com
80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Performance counter support for POWER10 processors.
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*
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* Copyright 2020 Madhavan Srinivasan, IBM Corporation.
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* Copyright 2020 Athira Rajeev, IBM Corporation.
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*/
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/*
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* Power10 event codes.
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*/
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EVENT(PM_CYC, 0x600f4);
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EVENT(PM_DISP_STALL_CYC, 0x100f8);
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EVENT(PM_EXEC_STALL, 0x30008);
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EVENT(PM_INST_CMPL, 0x500fa);
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EVENT(PM_BR_CMPL, 0x4d05e);
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EVENT(PM_BR_MPRED_CMPL, 0x400f6);
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EVENT(PM_BR_FIN, 0x2f04a);
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EVENT(PM_MPRED_BR_FIN, 0x3e098);
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EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0);
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/* All L1 D cache load references counted at finish, gated by reject */
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EVENT(PM_LD_REF_L1, 0x100fc);
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/* Load Missed L1 */
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EVENT(PM_LD_MISS_L1, 0x3e054);
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/* Store Missed L1 */
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EVENT(PM_ST_MISS_L1, 0x300f0);
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/* L1 cache data prefetches */
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EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c);
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fc);
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/* Instruction fetches from L1 */
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EVENT(PM_INST_FROM_L1, 0x04080);
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/* Instruction Demand sectors wriittent into IL1 */
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EVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040);
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/* Instruction prefetch written into IL1 */
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EVENT(PM_IC_PREF_REQ, 0x040a0);
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/* The data cache was reloaded from local core's L3 due to a demand load */
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EVENT(PM_DATA_FROM_L3, 0x01340000001c040);
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe);
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/* All successful D-side store dispatches for this thread */
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EVENT(PM_L2_ST, 0x010000046080);
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/* All successful D-side store dispatches for this thread that were L2 Miss */
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EVENT(PM_L2_ST_MISS, 0x26880);
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/* Total HW L3 prefetches(Load+store) */
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EVENT(PM_L3_PF_MISS_L3, 0x100000016080);
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/* Data PTEG reload */
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EVENT(PM_DTLB_MISS, 0x300fc);
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/* ITLB Reloaded */
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EVENT(PM_ITLB_MISS, 0x400fc);
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EVENT(PM_CYC_ALT, 0x0001e);
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EVENT(PM_INST_CMPL_ALT, 0x00002);
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/*
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* Memory Access Events
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*
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* Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
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* To enable capturing of memory profiling, these MMCRA bits
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* needs to be programmed and corresponding raw event format
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* encoding.
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*
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* MMCRA bits encoding needed are
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* SM (Sampling Mode)
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* EM (Eligibility for Random Sampling)
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* TECE (Threshold Event Counter Event)
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* TS (Threshold Start Event)
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* TE (Threshold End Event)
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*
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* Corresponding Raw Encoding bits:
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* sample [EM,SM]
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* thresh_sel (TECE)
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* thresh start (TS)
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* thresh end (TE)
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*/
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EVENT(MEM_LOADS, 0x35340401e0);
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EVENT(MEM_STORES, 0x353c0401e0);
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