073ebebd18
Right now, we cannot have split PT locks because 8xx does not support SMP. But for the sake of documentation *why* 8xx is fine regarding what we documented in huge_pte_lockptr(), let's just add code to enforce it at the same time as documenting it. This should also make everybody who wants to copy from the 8xx approach of supporting such unusual ways of mapping hugetlb folios aware that it gets tricky once multiple page tables are involved. Link: https://lkml.kernel.org/r/20240726150728.3159964-4-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: Borislav Petkov <bp@alien8.de> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Christian Brauner <brauner@kernel.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Mike Rapoport (Microsoft) <rppt@kernel.org> Cc: Muchun Song <muchun.song@linux.dev> Cc: "Naveen N. Rao" <naveen.n.rao@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Oscar Salvador <osalvador@suse.de> Cc: Peter Xu <peterx@redhat.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
556 lines
14 KiB
C
556 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* This file contains common routines for dealing with free of page tables
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* Along with common page table handling code
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*
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* Derived from arch/powerpc/mm/tlb_64.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*/
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#include <linux/kernel.h>
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#include <linux/gfp.h>
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#include <linux/mm.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/hugetlb.h>
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#include <asm/pte-walk.h>
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#ifdef CONFIG_PPC64
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#define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD)
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#else
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#define PGD_ALIGN PAGE_SIZE
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#endif
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pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN);
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static inline int is_exec_fault(void)
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{
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return current->thread.regs && TRAP(current->thread.regs) == 0x400;
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}
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/* We only try to do i/d cache coherency on stuff that looks like
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* reasonably "normal" PTEs. We currently require a PTE to be present
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* and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
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* on userspace PTEs
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*/
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static inline int pte_looks_normal(pte_t pte, unsigned long addr)
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{
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if (pte_present(pte) && !pte_special(pte)) {
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if (pte_ci(pte))
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return 0;
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if (!is_kernel_addr(addr))
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return 1;
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}
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return 0;
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}
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static struct folio *maybe_pte_to_folio(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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if (unlikely(!pfn_valid(pfn)))
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return NULL;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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return NULL;
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return page_folio(page);
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}
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#ifdef CONFIG_PPC_BOOK3S
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/* Server-style MMU handles coherency when hashing if HW exec permission
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* is supposed per page (currently 64-bit only). If not, then, we always
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* flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
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* support falls into the same category.
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*/
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static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr)
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{
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pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
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if (pte_looks_normal(pte, addr) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
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cpu_has_feature(CPU_FTR_NOEXECUTE))) {
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struct folio *folio = maybe_pte_to_folio(pte);
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if (!folio)
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return pte;
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if (!test_bit(PG_dcache_clean, &folio->flags)) {
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flush_dcache_icache_folio(folio);
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set_bit(PG_dcache_clean, &folio->flags);
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}
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}
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return pte;
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}
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#else /* CONFIG_PPC_BOOK3S */
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static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr) { return pte; }
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#endif /* CONFIG_PPC_BOOK3S */
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/* Embedded type MMU with HW exec support. This is a bit more complicated
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* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
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* instead we "filter out" the exec permission for non clean pages.
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*
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* This is also called once for the folio. So only work with folio->flags here.
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*/
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static inline pte_t set_pte_filter(pte_t pte, unsigned long addr)
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{
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struct folio *folio;
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if (radix_enabled())
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return pte;
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
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return set_pte_filter_hash(pte, addr);
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/* No exec permission in the first place, move on */
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if (!pte_exec(pte) || !pte_looks_normal(pte, addr))
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return pte;
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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folio = maybe_pte_to_folio(pte);
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if (unlikely(!folio))
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return pte;
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/* If the page clean, we move on */
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if (test_bit(PG_dcache_clean, &folio->flags))
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return pte;
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/* If it's an exec fault, we flush the cache and make it clean */
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if (is_exec_fault()) {
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flush_dcache_icache_folio(folio);
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set_bit(PG_dcache_clean, &folio->flags);
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return pte;
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}
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/* Else, we filter out _PAGE_EXEC */
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return pte_exprotect(pte);
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}
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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struct folio *folio;
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
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return pte;
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
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return pte;
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/* So here, we only care about exec faults, as we use them
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* to recover lost _PAGE_EXEC and perform I$/D$ coherency
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* if necessary. Also if _PAGE_EXEC is already set, same deal,
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* we just bail out
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*/
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if (dirty || pte_exec(pte) || !is_exec_fault())
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return pte;
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#ifdef CONFIG_DEBUG_VM
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/* So this is an exec fault, _PAGE_EXEC is not set. If it was
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* an error we would have bailed out earlier in do_page_fault()
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* but let's make sure of it
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*/
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if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
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return pte;
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#endif /* CONFIG_DEBUG_VM */
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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folio = maybe_pte_to_folio(pte);
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if (unlikely(!folio))
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goto bail;
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/* If the page is already clean, we move on */
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if (test_bit(PG_dcache_clean, &folio->flags))
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goto bail;
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/* Clean the page and set PG_dcache_clean */
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flush_dcache_icache_folio(folio);
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set_bit(PG_dcache_clean, &folio->flags);
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bail:
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return pte_mkexec(pte);
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}
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/*
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* set_pte stores a linux PTE into the linux page table.
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*/
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void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte, unsigned int nr)
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{
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/* Note: mm->context.id might not yet have been assigned as
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* this context might not have been activated yet when this
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* is called. Filter the pte value and use the filtered value
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* to setup all the ptes in the range.
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*/
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pte = set_pte_filter(pte, addr);
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/*
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* We don't need to call arch_enter/leave_lazy_mmu_mode()
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* because we expect set_ptes to be only be used on not present
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* and not hw_valid ptes. Hence there is no translation cache flush
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* involved that need to be batched.
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*/
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for (;;) {
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
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/* Perform the setting of the PTE */
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__set_pte_at(mm, addr, ptep, pte, 0);
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if (--nr == 0)
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break;
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ptep++;
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addr += PAGE_SIZE;
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pte = pte_next_pfn(pte);
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}
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}
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void unmap_kernel_page(unsigned long va)
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{
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pmd_t *pmdp = pmd_off_k(va);
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pte_t *ptep = pte_offset_kernel(pmdp, va);
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pte_clear(&init_mm, va, ptep);
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flush_tlb_kernel_range(va, va + PAGE_SIZE);
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}
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/*
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* This is called when relaxing access to a PTE. It's also called in the page
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* fault path when we don't hit any of the major fault cases, ie, a minor
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* update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
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* handled those two for us, we additionally deal with missing execute
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* permission here on some processors
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*/
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int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty)
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{
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int changed;
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entry = set_access_flags_filter(entry, vma, dirty);
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changed = !pte_same(*(ptep), entry);
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if (changed) {
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assert_pte_locked(vma->vm_mm, address);
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__ptep_set_access_flags(vma, ptep, entry,
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address, mmu_virtual_psize);
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}
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return changed;
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}
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#ifdef CONFIG_HUGETLB_PAGE
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int huge_ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t pte, int dirty)
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{
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#ifdef HUGETLB_NEED_PRELOAD
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/*
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* The "return 1" forces a call of update_mmu_cache, which will write a
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* TLB entry. Without this, platforms that don't do a write of the TLB
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* entry in the TLB miss handler asm will fault ad infinitum.
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*/
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ptep_set_access_flags(vma, addr, ptep, pte, dirty);
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return 1;
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#else
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int changed, psize;
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pte = set_access_flags_filter(pte, vma, dirty);
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changed = !pte_same(*(ptep), pte);
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if (changed) {
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#ifdef CONFIG_PPC_BOOK3S_64
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struct hstate *h = hstate_vma(vma);
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psize = hstate_get_psize(h);
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#ifdef CONFIG_DEBUG_VM
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assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
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#endif
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#else
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/*
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* Not used on non book3s64 platforms.
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* 8xx compares it with mmu_virtual_psize to
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* know if it is a huge page or not.
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*/
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psize = MMU_PAGE_COUNT;
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#endif
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__ptep_set_access_flags(vma, ptep, pte, addr, psize);
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}
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return changed;
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#endif
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}
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#if defined(CONFIG_PPC_8xx)
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#if defined(CONFIG_SPLIT_PTE_PTLOCKS) || defined(CONFIG_SPLIT_PMD_PTLOCKS)
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/* We need the same lock to protect the PMD table and the two PTE tables. */
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#error "8M hugetlb folios are incompatible with split page table locks"
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#endif
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static void __set_huge_pte_at(pmd_t *pmd, pte_t *ptep, pte_basic_t val)
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{
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pte_basic_t *entry = (pte_basic_t *)ptep;
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int num, i;
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
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num = number_of_cells_per_pte(pmd, val, 1);
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for (i = 0; i < num; i++, entry++, val += SZ_4K)
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*entry = val;
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}
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void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte, unsigned long sz)
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{
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pmd_t *pmdp = pmd_off(mm, addr);
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pte = set_pte_filter(pte, addr);
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if (sz == SZ_8M) { /* Flag both PMD entries as 8M and fill both page tables */
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*pmdp = __pmd(pmd_val(*pmdp) | _PMD_PAGE_8M);
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*(pmdp + 1) = __pmd(pmd_val(*(pmdp + 1)) | _PMD_PAGE_8M);
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__set_huge_pte_at(pmdp, pte_offset_kernel(pmdp, 0), pte_val(pte));
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__set_huge_pte_at(pmdp, pte_offset_kernel(pmdp + 1, 0), pte_val(pte) + SZ_4M);
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} else {
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__set_huge_pte_at(pmdp, ptep, pte_val(pte));
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}
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}
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#else
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void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte, unsigned long sz)
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{
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unsigned long pdsize;
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int i;
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pte = set_pte_filter(pte, addr);
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/*
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* Make sure hardware valid bit is not set. We don't do
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* tlb flush for this update.
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*/
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VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
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if (sz < PMD_SIZE)
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pdsize = PAGE_SIZE;
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else if (sz < PUD_SIZE)
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pdsize = PMD_SIZE;
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else if (sz < P4D_SIZE)
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pdsize = PUD_SIZE;
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else if (sz < PGDIR_SIZE)
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pdsize = P4D_SIZE;
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else
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pdsize = PGDIR_SIZE;
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for (i = 0; i < sz / pdsize; i++, ptep++, addr += pdsize) {
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__set_pte_at(mm, addr, ptep, pte, 0);
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pte = __pte(pte_val(pte) + ((unsigned long long)pdsize / PAGE_SIZE << PFN_PTE_SHIFT));
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}
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}
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#endif
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#endif /* CONFIG_HUGETLB_PAGE */
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#ifdef CONFIG_DEBUG_VM
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void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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pgd_t *pgd;
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p4d_t *p4d;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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spinlock_t *ptl;
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if (mm == &init_mm)
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return;
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pgd = mm->pgd + pgd_index(addr);
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BUG_ON(pgd_none(*pgd));
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p4d = p4d_offset(pgd, addr);
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BUG_ON(p4d_none(*p4d));
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pud = pud_offset(p4d, addr);
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BUG_ON(pud_none(*pud));
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pmd = pmd_offset(pud, addr);
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/*
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* khugepaged to collapse normal pages to hugepage, first set
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* pmd to none to force page fault/gup to take mmap_lock. After
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* pmd is set to none, we do a pte_clear which does this assertion
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* so if we find pmd none, return.
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*/
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if (pmd_none(*pmd))
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return;
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pte = pte_offset_map_nolock(mm, pmd, addr, &ptl);
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BUG_ON(!pte);
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assert_spin_locked(ptl);
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pte_unmap(pte);
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}
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#endif /* CONFIG_DEBUG_VM */
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unsigned long vmalloc_to_phys(void *va)
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{
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unsigned long pfn = vmalloc_to_pfn(va);
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BUG_ON(!pfn);
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return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
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}
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EXPORT_SYMBOL_GPL(vmalloc_to_phys);
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/*
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* We have 3 cases for pgds and pmds:
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* (1) invalid (all zeroes)
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* (2) pointer to next table, as normal; bottom 6 bits == 0
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* (3) leaf pte for huge page _PAGE_PTE set
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*
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* So long as we atomically load page table pointers we are safe against teardown,
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* we can follow the address down to the page and take a ref on it.
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* This function need to be called with interrupts disabled. We use this variant
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* when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
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*/
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pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
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bool *is_thp, unsigned *hpage_shift)
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{
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pgd_t *pgdp;
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#ifdef CONFIG_PPC64
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p4d_t p4d, *p4dp;
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pud_t pud, *pudp;
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#endif
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pmd_t pmd, *pmdp;
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pte_t *ret_pte;
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unsigned pdshift;
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if (hpage_shift)
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*hpage_shift = 0;
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if (is_thp)
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*is_thp = false;
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/*
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* Always operate on the local stack value. This make sure the
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* value don't get updated by a parallel THP split/collapse,
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* page fault or a page unmap. The return pte_t * is still not
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* stable. So should be checked there for above conditions.
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* Top level is an exception because it is folded into p4d.
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*
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* On PPC32, P4D/PUD/PMD are folded into PGD so go straight to
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* PMD level.
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*/
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pgdp = pgdir + pgd_index(ea);
|
|
#ifdef CONFIG_PPC64
|
|
p4dp = p4d_offset(pgdp, ea);
|
|
p4d = READ_ONCE(*p4dp);
|
|
pdshift = P4D_SHIFT;
|
|
|
|
if (p4d_none(p4d))
|
|
return NULL;
|
|
|
|
if (p4d_leaf(p4d)) {
|
|
ret_pte = (pte_t *)p4dp;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Even if we end up with an unmap, the pgtable will not
|
|
* be freed, because we do an rcu free and here we are
|
|
* irq disabled
|
|
*/
|
|
pdshift = PUD_SHIFT;
|
|
pudp = pud_offset(&p4d, ea);
|
|
pud = READ_ONCE(*pudp);
|
|
|
|
if (pud_none(pud))
|
|
return NULL;
|
|
|
|
if (pud_leaf(pud)) {
|
|
ret_pte = (pte_t *)pudp;
|
|
goto out;
|
|
}
|
|
|
|
pmdp = pmd_offset(&pud, ea);
|
|
#else
|
|
pmdp = pmd_offset(pud_offset(p4d_offset(pgdp, ea), ea), ea);
|
|
#endif
|
|
pdshift = PMD_SHIFT;
|
|
pmd = READ_ONCE(*pmdp);
|
|
|
|
/*
|
|
* A hugepage collapse is captured by this condition, see
|
|
* pmdp_collapse_flush.
|
|
*/
|
|
if (pmd_none(pmd))
|
|
return NULL;
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
/*
|
|
* A hugepage split is captured by this condition, see
|
|
* pmdp_invalidate.
|
|
*
|
|
* Huge page modification can be caught here too.
|
|
*/
|
|
if (pmd_is_serializing(pmd))
|
|
return NULL;
|
|
#endif
|
|
|
|
if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
|
|
if (is_thp)
|
|
*is_thp = true;
|
|
ret_pte = (pte_t *)pmdp;
|
|
goto out;
|
|
}
|
|
|
|
if (pmd_leaf(pmd)) {
|
|
ret_pte = (pte_t *)pmdp;
|
|
goto out;
|
|
}
|
|
|
|
return pte_offset_kernel(&pmd, ea);
|
|
|
|
out:
|
|
if (hpage_shift)
|
|
*hpage_shift = pdshift;
|
|
return ret_pte;
|
|
}
|
|
EXPORT_SYMBOL_GPL(__find_linux_pte);
|
|
|
|
/* Note due to the way vm flags are laid out, the bits are XWR */
|
|
const pgprot_t protection_map[16] = {
|
|
[VM_NONE] = PAGE_NONE,
|
|
[VM_READ] = PAGE_READONLY,
|
|
[VM_WRITE] = PAGE_COPY,
|
|
[VM_WRITE | VM_READ] = PAGE_COPY,
|
|
[VM_EXEC] = PAGE_EXECONLY_X,
|
|
[VM_EXEC | VM_READ] = PAGE_READONLY_X,
|
|
[VM_EXEC | VM_WRITE] = PAGE_COPY_X,
|
|
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_X,
|
|
[VM_SHARED] = PAGE_NONE,
|
|
[VM_SHARED | VM_READ] = PAGE_READONLY,
|
|
[VM_SHARED | VM_WRITE] = PAGE_SHARED,
|
|
[VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED,
|
|
[VM_SHARED | VM_EXEC] = PAGE_EXECONLY_X,
|
|
[VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X,
|
|
[VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_X,
|
|
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X
|
|
};
|
|
|
|
#ifndef CONFIG_PPC_BOOK3S_64
|
|
DECLARE_VM_GET_PAGE_PROT
|
|
#endif
|