1a59d1b8e0
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2005 Tundra Semiconductor Corp.
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* Alex Bounine, <alexandreb at tundra.com).
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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/*
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* definitions for interrupt controller initialization and external interrupt
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* demultiplexing on TSI108EMU/SVB boards.
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*/
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#ifndef _ASM_POWERPC_TSI108_IRQ_H
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#define _ASM_POWERPC_TSI108_IRQ_H
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/*
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* Tsi108 interrupts
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*/
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#ifndef TSI108_IRQ_REG_BASE
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#define TSI108_IRQ_REG_BASE 0
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#endif
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#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
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#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
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#define MAX_TASK_PRIO 0xF
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#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
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#define DEFAULT_PRIO_LVL 10 /* initial priority level */
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/* Interrupt vectors assignment to external and internal
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* sources of requests. */
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/* EXTERNAL INTERRUPT SOURCES */
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#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
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#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
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#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
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#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
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/* INTERNAL INTERRUPT SOURCES */
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#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
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#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
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#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
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#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
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#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
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#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
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#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
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#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
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#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
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#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
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#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
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#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
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#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
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#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
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#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
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#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
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#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
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#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
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#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
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#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
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#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
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#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
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#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
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#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
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#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
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#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
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#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
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#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
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#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
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#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
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#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
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#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
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/*
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* PCI bus INTA# - INTD# lines demultiplexor
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*/
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#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
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#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
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#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
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#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
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#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
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#define NUM_PCI_IRQS (4)
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/* number of entries in vector dispatch table */
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#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
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/* Mapping of MPIC outputs to processors' interrupt pins */
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#define IDIR_INT_OUT0 0x1
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#define IDIR_INT_OUT1 0x2
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#define IDIR_INT_OUT2 0x4
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#define IDIR_INT_OUT3 0x8
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/*---------------------------------------------------------------
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* IRQ line configuration parameters */
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/* Interrupt delivery modes */
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typedef enum {
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TSI108_IRQ_DIRECTED,
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TSI108_IRQ_DISTRIBUTED,
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} TSI108_IRQ_MODE;
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#endif /* _ASM_POWERPC_TSI108_IRQ_H */
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