2f9060b1db
Fix typos, most reported by "codespell arch/mips". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-mips@vger.kernel.org Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
43 lines
1005 B
ArmAsm
43 lines
1005 B
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995 - 1999 Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*
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* Cache error handler
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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/*
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* Game over. Go to the button. Press gently. Swear where allowed by
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* legislation.
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*/
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LEAF(except_vec2_generic)
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.set noreorder
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.set noat
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.set mips0
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/*
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* This is a very bad place to be. Our cache error
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* detection has triggered. If we have write-back data
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* in the cache, we may not be able to recover. As a
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* first-order desperate measure, turn off KSEG0 caching.
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*/
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mfc0 k0,CP0_CONFIG
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li k1,~CONF_CM_CMASK
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and k0,k0,k1
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ori k0,k0,CONF_CM_UNCACHED
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mtc0 k0,CP0_CONFIG
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/* Give it a few cycles to sink in... */
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nop
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nop
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nop
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j cache_parity_error
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nop
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END(except_vec2_generic)
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