bb54e66099
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230717225358.3210536-1-robh@kernel.org Signed-off-by: Michal Simek <michal.simek@amd.com>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Zynq power management
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*
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* Copyright (C) 2012 - 2014 Xilinx
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*
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* Sören Brinkmann <soren.brinkmann@xilinx.com>
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "common.h"
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/* register offsets */
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#define DDRC_CTRL_REG1_OFFS 0x60
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#define DDRC_DRAM_PARAM_REG3_OFFS 0x20
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/* bitfields */
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#define DDRC_CLOCKSTOP_MASK BIT(23)
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#define DDRC_SELFREFRESH_MASK BIT(12)
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static void __iomem *ddrc_base;
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/**
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* zynq_pm_ioremap() - Create IO mappings
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* @comp: DT compatible string
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* Return: Pointer to the mapped memory or NULL.
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*
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* Remap the memory region for a compatible DT node.
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*/
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static void __iomem *zynq_pm_ioremap(const char *comp)
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{
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struct device_node *np;
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void __iomem *base = NULL;
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np = of_find_compatible_node(NULL, NULL, comp);
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if (np) {
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base = of_iomap(np, 0);
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of_node_put(np);
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} else {
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pr_warn("%s: no compatible node found for '%s'\n", __func__,
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comp);
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}
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return base;
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}
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/**
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* zynq_pm_late_init() - Power management init
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*
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* Initialization of power management related features and infrastructure.
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*/
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void __init zynq_pm_late_init(void)
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{
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u32 reg;
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ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
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if (!ddrc_base) {
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pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
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} else {
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/*
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* Enable DDRC clock stop feature. The HW takes care of
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* entering/exiting the correct mode depending
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* on activity state.
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*/
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reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
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reg |= DDRC_CLOCKSTOP_MASK;
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writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
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}
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}
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