24e44913aa
SoC platform changes. Main theme this merge window:
- The Netx platform (Netx 100/500) platform is removed by Linus Walleij--
the SoC doesn't have active maintainers with hardware, and in
discussions with the vendor the agreement was that it's OK to remove.
- Russell King has a series of patches that cleans up and refactors
SA1101 and RiscPC support.
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yKOgPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3SNEP/iJsMeeunX0P7Ym3zNFjykhspkkUmo7sEKuz
NBcexnQpkm+OLgjfwT7j3kXvOs4mzMzH56J6h7dEDSHbQP1MDIgpMw6OEzMMsQTV
XL1AWz1IO7Sq/mG17daPs9c75o6NYQ7pSEd/ncbjKuJQOpGsi4DyrVrhk9WdzYl2
hcs4XOzOMZgDTsXHVdWkfpHazpWxEXPCD7v5bt6ueU0YnT3csUbzOTTvw+55JxRV
fYz0lg4wTMRYMQMOejpx1HXwdmbVOHLUYkCxcLUaVqMnm88q/IddJVklBbPGWAU5
Z4gFpL+FxcFhEZtu28CoubPYzf/mHDk8Ry2UWwBiRwiGoKfblomI1fpnbyrX53aE
lpO5p7MfOVVV2WNxpbUND+ilbgKOREfRHd314GLPUjwudp2sTuDRZ1GAbt3JwsIM
L1HesyjCtb6itCSwGsmmGsX2Wvu+WT7slpsYwHs2qklE/X1zQq0R4Jf2xUNpwqPb
FqGZAtc6CCQtyF/Mcpp6OQd+cV0tgQVIw7teKol/xR1dSzN/+1zO1J9UHk9/dWUU
sb5lGa/AtBrIbWxS1qLuA5bgyDqxXYDZi0y/Bu1qMHYebRW37z9kvomtzBiMNX2o
SAxvr9iGPlTxTjGjRCyBVFmsbCMYLabNoL9tuuXvo+DnjFoOilTef+qePOv7ZYZX
kwUyS2eu
=FX6e
-----END PGP SIGNATURE-----
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC platform updates from Olof Johansson:
"SoC platform changes. Main theme this merge window:
- The Netx platform (Netx 100/500) platform is removed by Linus
Walleij-- the SoC doesn't have active maintainers with hardware,
and in discussions with the vendor the agreement was that it's OK
to remove.
- Russell King has a series of patches that cleans up and refactors
SA1101 and RiscPC support"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
ARM: stm32: use "depends on" instead of "if" after prompt
ARM: sa1100: convert to common clock framework
ARM: exynos: Cleanup cppcheck shifting warning
ARM: pxa/lubbock: remove lubbock_set_misc_wr() from global view
ARM: exynos: Only build MCPM support if used
arm: add missing include platform-data/atmel.h
ARM: davinci: Use GPIO lookup table for DA850 LEDs
ARM: OMAP2: drop explicit assembler architecture
ARM: use arch_extension directive instead of arch argument
ARM: imx: Switch imx7d to imx-cpufreq-dt for speed-grading
ARM: bcm: Enable PINCTRL for ARCH_BRCMSTB
ARM: bcm: Enable ARCH_HAS_RESET_CONTROLLER for ARCH_BRCMSTB
ARM: riscpc: enable chained scatterlist support
ARM: riscpc: reduce IRQ handling code
ARM: riscpc: move RiscPC assembly files from arch/arm/lib to mach-rpc
ARM: riscpc: parse video information from tagged list
ARM: riscpc: add ecard quirk for Atomwide 3port serial card
MAINTAINERS: mvebu: Add git entry
soc: ti: pm33xx: Add a print while entering RTC only mode with DDR in self-refresh
ARM: OMAP2+: Make some variables static
...
134 lines
3.5 KiB
ArmAsm
134 lines
3.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Secondary CPU startup routine source file.
|
|
*
|
|
* Copyright (C) 2009-2014 Texas Instruments, Inc.
|
|
*
|
|
* Author:
|
|
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
*
|
|
* Interface functions needed for the SMP. This file is based on arm
|
|
* realview smp platform.
|
|
* Copyright (c) 2003 ARM Limited.
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <linux/init.h>
|
|
#include <asm/assembler.h>
|
|
|
|
#include "omap44xx.h"
|
|
|
|
/* Physical address needed since MMU not enabled yet on secondary core */
|
|
#define AUX_CORE_BOOT0_PA 0x48281800
|
|
#define API_HYP_ENTRY 0x102
|
|
|
|
ENTRY(omap_secondary_startup)
|
|
#ifdef CONFIG_SMP
|
|
b secondary_startup
|
|
#else
|
|
/* Should never get here */
|
|
again: wfi
|
|
b again
|
|
#endif
|
|
#ENDPROC(omap_secondary_startup)
|
|
|
|
/*
|
|
* OMAP5 specific entry point for secondary CPU to jump from ROM
|
|
* code. This routine also provides a holding flag into which
|
|
* secondary core is held until we're ready for it to initialise.
|
|
* The primary core will update this flag using a hardware
|
|
* register AuxCoreBoot0.
|
|
*/
|
|
ENTRY(omap5_secondary_startup)
|
|
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
|
ldr r0, [r2]
|
|
mov r0, r0, lsr #5
|
|
mrc p15, 0, r4, c0, c0, 5
|
|
and r4, r4, #0x0f
|
|
cmp r0, r4
|
|
bne wait
|
|
b omap_secondary_startup
|
|
ENDPROC(omap5_secondary_startup)
|
|
/*
|
|
* Same as omap5_secondary_startup except we call into the ROM to
|
|
* enable HYP mode first. This is called instead of
|
|
* omap5_secondary_startup if the primary CPU was put into HYP mode by
|
|
* the boot loader.
|
|
*/
|
|
.arch armv7-a
|
|
.arch_extension sec
|
|
ENTRY(omap5_secondary_hyp_startup)
|
|
wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
|
ldr r0, [r2]
|
|
mov r0, r0, lsr #5
|
|
mrc p15, 0, r4, c0, c0, 5
|
|
and r4, r4, #0x0f
|
|
cmp r0, r4
|
|
bne wait_2
|
|
ldr r12, =API_HYP_ENTRY
|
|
badr r0, hyp_boot
|
|
smc #0
|
|
hyp_boot:
|
|
b omap_secondary_startup
|
|
ENDPROC(omap5_secondary_hyp_startup)
|
|
/*
|
|
* OMAP4 specific entry point for secondary CPU to jump from ROM
|
|
* code. This routine also provides a holding flag into which
|
|
* secondary core is held until we're ready for it to initialise.
|
|
* The primary core will update this flag using a hardware
|
|
* register AuxCoreBoot0.
|
|
*/
|
|
ENTRY(omap4_secondary_startup)
|
|
hold: ldr r12,=0x103
|
|
dsb
|
|
smc #0 @ read from AuxCoreBoot0
|
|
mov r0, r0, lsr #9
|
|
mrc p15, 0, r4, c0, c0, 5
|
|
and r4, r4, #0x0f
|
|
cmp r0, r4
|
|
bne hold
|
|
|
|
/*
|
|
* we've been released from the wait loop,secondary_stack
|
|
* should now contain the SVC stack for this core
|
|
*/
|
|
b omap_secondary_startup
|
|
ENDPROC(omap4_secondary_startup)
|
|
|
|
ENTRY(omap4460_secondary_startup)
|
|
hold_2: ldr r12,=0x103
|
|
dsb
|
|
smc #0 @ read from AuxCoreBoot0
|
|
mov r0, r0, lsr #9
|
|
mrc p15, 0, r4, c0, c0, 5
|
|
and r4, r4, #0x0f
|
|
cmp r0, r4
|
|
bne hold_2
|
|
|
|
/*
|
|
* GIC distributor control register has changed between
|
|
* CortexA9 r1pX and r2pX. The Control Register secure
|
|
* banked version is now composed of 2 bits:
|
|
* bit 0 == Secure Enable
|
|
* bit 1 == Non-Secure Enable
|
|
* The Non-Secure banked register has not changed
|
|
* Because the ROM Code is based on the r1pX GIC, the CPU1
|
|
* GIC restoration will cause a problem to CPU0 Non-Secure SW.
|
|
* The workaround must be:
|
|
* 1) Before doing the CPU1 wakeup, CPU0 must disable
|
|
* the GIC distributor
|
|
* 2) CPU1 must re-enable the GIC distributor on
|
|
* it's wakeup path.
|
|
*/
|
|
ldr r1, =OMAP44XX_GIC_DIST_BASE
|
|
ldr r0, [r1]
|
|
orr r0, #1
|
|
str r0, [r1]
|
|
|
|
/*
|
|
* we've been released from the wait loop,secondary_stack
|
|
* should now contain the SVC stack for this core
|
|
*/
|
|
b omap_secondary_startup
|
|
ENDPROC(omap4460_secondary_startup)
|