52e6676ef5
Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it
under the terms of the gnu general public license as published by the
free software foundation version 2 this program is distributed as is
without any warranty of any kind whether express or implied without
even the implied warranty of merchantability or fitness for a
particular purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
215 lines
5.8 KiB
C
215 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TI81XX Clock Domain data.
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*
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* Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
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* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm81xx.h"
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/*
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* Note that 814x seems to have HWSUP_SWSUP for many clockdomains
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* while 816x does not. According to the TRM, 816x only has HWSUP
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* for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
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* seems to have the related ifdef the wrong way around claiming
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* 816x supports HWSUP while 814x does not. For now, we only set
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* HWSUP for ALWON_L3_FAST as that seems to be supported for both
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* dm814x and dm816x.
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*/
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/* Common for 81xx */
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static struct clockdomain alwon_l3_slow_81xx_clkdm = {
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.name = "alwon_l3s_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_med_81xx_clkdm = {
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.name = "alwon_l3_med_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_fast_81xx_clkdm = {
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.name = "alwon_l3_fast_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain alwon_ethernet_81xx_clkdm = {
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.name = "alwon_ethernet_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_81xx_clkdm = {
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.name = "mmu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_cfg_81xx_clkdm = {
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.name = "mmu_cfg_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_l3_slow_81xx_clkdm = {
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.name = "default_l3_slow_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI81XX_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_sata_81xx_clkdm = {
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.name = "default_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI81XX_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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/* 816x only */
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static struct clockdomain alwon_mpu_816x_clkdm = {
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.name = "alwon_mpu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain active_gem_816x_clkdm = {
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.name = "active_gem_clkdm",
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.pwrdm = { .name = "active_pwrdm" },
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.cm_inst = TI81XX_CM_ACTIVE_MOD,
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.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd0_816x_clkdm = {
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.name = "ivahd0_clkdm",
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.pwrdm = { .name = "ivahd0_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD0_MOD,
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.clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd1_816x_clkdm = {
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.name = "ivahd1_clkdm",
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.pwrdm = { .name = "ivahd1_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD1_MOD,
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.clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd2_816x_clkdm = {
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.name = "ivahd2_clkdm",
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.pwrdm = { .name = "ivahd2_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD2_MOD,
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.clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain sgx_816x_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.cm_inst = TI81XX_CM_SGX_MOD,
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.clkdm_offs = TI816X_CM_SGX_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_l3_med_816x_clkdm = {
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.name = "default_l3_med_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI81XX_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_ducati_816x_clkdm = {
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.name = "default_ducati_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI81XX_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_pci_816x_clkdm = {
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.name = "default_pci_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI81XX_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain *clockdomains_ti814x[] __initdata = {
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&alwon_l3_slow_81xx_clkdm,
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&alwon_l3_med_81xx_clkdm,
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&alwon_l3_fast_81xx_clkdm,
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&alwon_ethernet_81xx_clkdm,
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&mmu_81xx_clkdm,
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&mmu_cfg_81xx_clkdm,
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&default_l3_slow_81xx_clkdm,
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&default_sata_81xx_clkdm,
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NULL,
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};
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void __init ti814x_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am33xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_ti814x);
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clkdm_complete_init();
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}
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static struct clockdomain *clockdomains_ti816x[] __initdata = {
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&alwon_mpu_816x_clkdm,
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&alwon_l3_slow_81xx_clkdm,
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&alwon_l3_med_81xx_clkdm,
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&alwon_l3_fast_81xx_clkdm,
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&alwon_ethernet_81xx_clkdm,
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&mmu_81xx_clkdm,
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&mmu_cfg_81xx_clkdm,
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&active_gem_816x_clkdm,
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&ivahd0_816x_clkdm,
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&ivahd1_816x_clkdm,
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&ivahd2_816x_clkdm,
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&sgx_816x_clkdm,
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&default_l3_med_816x_clkdm,
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&default_ducati_816x_clkdm,
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&default_pci_816x_clkdm,
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&default_l3_slow_81xx_clkdm,
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&default_sata_81xx_clkdm,
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NULL,
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};
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void __init ti816x_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am33xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_ti816x);
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clkdm_complete_init();
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}
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#endif
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