7af5b901e8
With LPAE enabled, privileged no-access cannot be enforced using CPU domains as such feature is not available. This patch implements PAN by disabling TTBR0 page table walks while in kernel mode. The ARM architecture allows page table walks to be split between TTBR0 and TTBR1. With LPAE enabled, the split is defined by a combination of TTBCR T0SZ and T1SZ bits. Currently, an LPAE-enabled kernel uses TTBR0 for user addresses and TTBR1 for kernel addresses with the VMSPLIT_2G and VMSPLIT_3G configurations. The main advantage for the 3:1 split is that TTBR1 is reduced to 2 levels, so potentially faster TLB refill (though usually the first level entries are already cached in the TLB). The PAN support on LPAE-enabled kernels uses TTBR0 when running in user space or in kernel space during user access routines (TTBCR T0SZ and T1SZ are both 0). When running user accesses are disabled in kernel mode, TTBR0 page table walks are disabled by setting TTBCR.EPD0. TTBR1 is used for kernel accesses (including loadable modules; anything covered by swapper_pg_dir) by reducing the TTBCR.T0SZ to the minimum (2^(32-7) = 32MB). To avoid user accesses potentially hitting stale TLB entries, the ASID is switched to 0 (reserved) by setting TTBCR.A1 and using the ASID value in TTBR1. The difference from a non-PAN kernel is that with the 3:1 memory split, TTBR1 always uses 3 levels of page tables. As part of the change we are using preprocessor elif definied() clauses so balance these clauses by converting relevant precedingt ifdef clauses to if defined() clauses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
177 lines
7.0 KiB
C
177 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1995-2003 Russell King
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* 2001-2002 Keith Owens
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*
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* Generate definitions needed by assembly language modules.
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* This code generates raw asm output which is post-processed to extract
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* and format the required data.
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*/
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <asm/cacheflush.h>
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#include <asm/kexec-internal.h>
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#include <asm/glue-df.h>
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#include <asm/glue-pf.h>
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#include <asm/mach/arch.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/mpu.h>
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#include <asm/procinfo.h>
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#include <asm/suspend.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <linux/kbuild.h>
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#include <linux/arm-smccc.h>
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#include <vdso/datapage.h>
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#include "signal.h"
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/*
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* Make sure that the compiler and target are compatible.
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*/
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#if defined(__APCS_26__)
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#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
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#endif
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int main(void)
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{
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DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
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#ifdef CONFIG_STACKPROTECTOR
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DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
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#endif
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BLANK();
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DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
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DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
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DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
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DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
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DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
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DEFINE(TI_ABI_SYSCALL, offsetof(struct thread_info, abi_syscall));
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DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
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DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
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#ifdef CONFIG_VFP
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DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
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#ifdef CONFIG_SMP
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DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
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#endif
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#endif
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DEFINE(SOFTIRQ_DISABLE_OFFSET,SOFTIRQ_DISABLE_OFFSET);
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#ifdef CONFIG_ARM_THUMBEE
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DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
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#endif
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#ifdef CONFIG_IWMMXT
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DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
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#endif
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BLANK();
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DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0));
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DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1));
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DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2));
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DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3));
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DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4));
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DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5));
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DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6));
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DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7));
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DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8));
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DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9));
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DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10));
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DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp));
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DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip));
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DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp));
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DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr));
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DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc));
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DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr));
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DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
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DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
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DEFINE(SVC_DACR, offsetof(struct svc_pt_regs, dacr));
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DEFINE(SVC_TTBCR, offsetof(struct svc_pt_regs, ttbcr));
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DEFINE(SVC_REGS_SIZE, sizeof(struct svc_pt_regs));
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BLANK();
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DEFINE(SIGFRAME_RC3_OFFSET, offsetof(struct sigframe, retcode[3]));
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DEFINE(RT_SIGFRAME_RC3_OFFSET, offsetof(struct rt_sigframe, sig.retcode[3]));
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BLANK();
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#ifdef CONFIG_CACHE_L2X0
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DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
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DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
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DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
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DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
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DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
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DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
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DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
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DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl));
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BLANK();
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#endif
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#ifdef CONFIG_CPU_HAS_ASID
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
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BLANK();
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#endif
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DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
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DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
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BLANK();
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DEFINE(VM_EXEC, VM_EXEC);
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BLANK();
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DEFINE(PAGE_SZ, PAGE_SIZE);
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BLANK();
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DEFINE(SYS_ERROR0, 0x9f0000);
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BLANK();
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DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc));
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DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr));
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DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name));
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BLANK();
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DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
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DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
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DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
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DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
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BLANK();
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#ifdef MULTI_DABORT
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DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort));
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#endif
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#ifdef MULTI_PABORT
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DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
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#endif
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#ifdef MULTI_CPU
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DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size));
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DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend));
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DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume));
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#endif
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#ifdef MULTI_CACHE
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DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all));
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#endif
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#ifdef CONFIG_ARM_CPU_SUSPEND
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DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
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DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
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DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));
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#endif
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DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
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DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
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BLANK();
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DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
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DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
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DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
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BLANK();
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DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
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DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
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BLANK();
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#ifdef CONFIG_VDSO
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DEFINE(VDSO_DATA_SIZE, sizeof(union vdso_data_store));
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#endif
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BLANK();
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#ifdef CONFIG_ARM_MPU
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DEFINE(MPU_RNG_INFO_RNGS, offsetof(struct mpu_rgn_info, rgns));
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DEFINE(MPU_RNG_INFO_USED, offsetof(struct mpu_rgn_info, used));
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DEFINE(MPU_RNG_SIZE, sizeof(struct mpu_rgn));
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DEFINE(MPU_RGN_DRBAR, offsetof(struct mpu_rgn, drbar));
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DEFINE(MPU_RGN_DRSR, offsetof(struct mpu_rgn, drsr));
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DEFINE(MPU_RGN_DRACR, offsetof(struct mpu_rgn, dracr));
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DEFINE(MPU_RGN_PRBAR, offsetof(struct mpu_rgn, prbar));
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DEFINE(MPU_RGN_PRLAR, offsetof(struct mpu_rgn, prlar));
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#endif
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DEFINE(KEXEC_START_ADDR, offsetof(struct kexec_relocate_data, kexec_start_address));
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DEFINE(KEXEC_INDIR_PAGE, offsetof(struct kexec_relocate_data, kexec_indirection_page));
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DEFINE(KEXEC_MACH_TYPE, offsetof(struct kexec_relocate_data, kexec_mach_type));
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DEFINE(KEXEC_R2, offsetof(struct kexec_relocate_data, kexec_r2));
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return 0;
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}
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