724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
757 lines
20 KiB
Plaintext
757 lines
20 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Erin.Lo <erin.lo@mediatek.com>
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*
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*/
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include "mt2701-pinfunc.h"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "mediatek,mt2701";
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interrupt-parent = <&cirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&thermal 0>;
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sustainable-power = <1000>;
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trips {
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threshold: trip-point@0 {
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temperature = <68000>;
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hysteresis = <2000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit@0 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2701-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt2701-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt2701-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: power-controller@10006000 {
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compatible = "mediatek,mt2701-scpsys", "syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt2701-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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pio: pinctrl@1000b000 {
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt2701-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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cirq: interrupt-controller@10204000 {
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compatible = "mediatek,mt2701-cirq",
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"mediatek,mtk-cirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&sysirq>;
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reg = <0 0x10204000 0 0x400>;
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mediatek,ext-irq-range = <32 200>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2701-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt2701-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt2701-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <0>;
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compatible = "mediatek,mt2701-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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nandc: nand-controller@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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status = "disabled";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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status = "disabled";
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};
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nor_flash: spi@11014000 {
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compatible = "mediatek,mt2701-nor",
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"mediatek,mt8173-nor";
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reg = <0 0x11014000 0 0xe0>;
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clocks = <&pericfg CLK_PERI_FLASH>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@11016000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11016000 0 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI1_SEL>,
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<&pericfg CLK_PERI_SPI1>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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spi2: spi@11017000 {
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compatible = "mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11017000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI2_SEL>,
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<&pericfg CLK_PERI_SPI2>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt2701-audsys", "syscon";
|
|
reg = <0 0x11220000 0 0x2000>;
|
|
#clock-cells = <1>;
|
|
|
|
afe: audio-controller {
|
|
compatible = "mediatek,mt2701-audio";
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "afe", "asys";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
|
|
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
|
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
|
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
|
<&topckgen CLK_TOP_AUD_48K_TIMING>,
|
|
<&topckgen CLK_TOP_AUD_44K_TIMING>,
|
|
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
|
|
<&audsys CLK_AUD_I2SO1>,
|
|
<&audsys CLK_AUD_I2SO2>,
|
|
<&audsys CLK_AUD_I2SO3>,
|
|
<&audsys CLK_AUD_I2SO4>,
|
|
<&audsys CLK_AUD_I2SIN1>,
|
|
<&audsys CLK_AUD_I2SIN2>,
|
|
<&audsys CLK_AUD_I2SIN3>,
|
|
<&audsys CLK_AUD_I2SIN4>,
|
|
<&audsys CLK_AUD_ASRCO1>,
|
|
<&audsys CLK_AUD_ASRCO2>,
|
|
<&audsys CLK_AUD_ASRCO3>,
|
|
<&audsys CLK_AUD_ASRCO4>,
|
|
<&audsys CLK_AUD_AFE>,
|
|
<&audsys CLK_AUD_AFE_CONN>,
|
|
<&audsys CLK_AUD_A1SYS>,
|
|
<&audsys CLK_AUD_A2SYS>,
|
|
<&audsys CLK_AUD_AFE_MRGIF>;
|
|
|
|
clock-names = "infra_sys_audio_clk",
|
|
"top_audio_mux1_sel",
|
|
"top_audio_mux2_sel",
|
|
"top_audio_a1sys_hp",
|
|
"top_audio_a2sys_hp",
|
|
"i2s0_src_sel",
|
|
"i2s1_src_sel",
|
|
"i2s2_src_sel",
|
|
"i2s3_src_sel",
|
|
"i2s0_src_div",
|
|
"i2s1_src_div",
|
|
"i2s2_src_div",
|
|
"i2s3_src_div",
|
|
"i2s0_mclk_en",
|
|
"i2s1_mclk_en",
|
|
"i2s2_mclk_en",
|
|
"i2s3_mclk_en",
|
|
"i2so0_hop_ck",
|
|
"i2so1_hop_ck",
|
|
"i2so2_hop_ck",
|
|
"i2so3_hop_ck",
|
|
"i2si0_hop_ck",
|
|
"i2si1_hop_ck",
|
|
"i2si2_hop_ck",
|
|
"i2si3_hop_ck",
|
|
"asrc0_out_ck",
|
|
"asrc1_out_ck",
|
|
"asrc2_out_ck",
|
|
"asrc3_out_ck",
|
|
"audio_afe_pd",
|
|
"audio_afe_conn_pd",
|
|
"audio_a1sys_pd",
|
|
"audio_a2sys_pd",
|
|
"audio_mrgif_pd";
|
|
|
|
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
|
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
|
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
|
|
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
|
|
<&topckgen CLK_TOP_AUD2PLL_90M>;
|
|
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
|
|
};
|
|
};
|
|
|
|
mmsys: syscon@14000000 {
|
|
compatible = "mediatek,mt2701-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
bls: pwm@1400a000 {
|
|
compatible = "mediatek,mt2701-disp-pwm";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
|
|
clock-names = "main", "mm";
|
|
status = "disabled";
|
|
};
|
|
|
|
larb0: larb@14010000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
mediatek,larb-id = <0>;
|
|
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
|
<&mmsys CLK_MM_SMI_LARB0>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
imgsys: syscon@15000000 {
|
|
compatible = "mediatek,mt2701-imgsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb2: larb@15001000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x15001000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
mediatek,larb-id = <2>;
|
|
clocks = <&imgsys CLK_IMG_SMI_COMM>,
|
|
<&imgsys CLK_IMG_SMI_COMM>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
|
};
|
|
|
|
jpegdec: jpegdec@15004000 {
|
|
compatible = "mediatek,mt2701-jpgdec";
|
|
reg = <0 0x15004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
|
|
<&imgsys CLK_IMG_JPGDEC>;
|
|
clock-names = "jpgdec-smi",
|
|
"jpgdec";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
|
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
|
|
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
|
|
};
|
|
|
|
jpegenc: jpegenc@1500a000 {
|
|
compatible = "mediatek,mt2701-jpgenc",
|
|
"mediatek,mtk-jpgenc";
|
|
reg = <0 0x1500a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys CLK_IMG_VENC>;
|
|
clock-names = "jpgenc";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
|
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
|
|
<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
|
|
};
|
|
|
|
vdecsys: syscon@16000000 {
|
|
compatible = "mediatek,mt2701-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
larb1: larb@16010000 {
|
|
compatible = "mediatek,mt2701-smi-larb";
|
|
reg = <0 0x16010000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
mediatek,larb-id = <1>;
|
|
clocks = <&vdecsys CLK_VDEC_CKGEN>,
|
|
<&vdecsys CLK_VDEC_LARB>;
|
|
clock-names = "apb", "smi";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
hifsys: syscon@1a000000 {
|
|
compatible = "mediatek,mt2701-hifsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
usb0: usb@1a1c0000 {
|
|
compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x1a1c0000 0 0x1000>,
|
|
<0 0x1a1c4700 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
|
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy0: t-phy@1a1c4000 {
|
|
compatible = "mediatek,mt2701-tphy",
|
|
"mediatek,generic-tphy-v1";
|
|
reg = <0 0x1a1c4000 0 0x0700>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port0: usb-phy@1a1c4800 {
|
|
reg = <0 0x1a1c4800 0 0x0100>;
|
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port0: usb-phy@1a1c4900 {
|
|
reg = <0 0x1a1c4900 0 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb1: usb@1a240000 {
|
|
compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x1a240000 0 0x1000>,
|
|
<0 0x1a244700 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
|
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "ref_ck";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy1: t-phy@1a244000 {
|
|
compatible = "mediatek,mt2701-tphy",
|
|
"mediatek,generic-tphy-v1";
|
|
reg = <0 0x1a244000 0 0x0700>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port1: usb-phy@1a244800 {
|
|
reg = <0 0x1a244800 0 0x0100>;
|
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port1: usb-phy@1a244900 {
|
|
reg = <0 0x1a244900 0 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb2: usb@11200000 {
|
|
compatible = "mediatek,mt2701-musb",
|
|
"mediatek,mtk-musb";
|
|
reg = <0 0x11200000 0 0x1000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "mc";
|
|
phys = <&u2port2 PHY_TYPE_USB2>;
|
|
dr_mode = "otg";
|
|
clocks = <&pericfg CLK_PERI_USB0>,
|
|
<&pericfg CLK_PERI_USB0_MCU>,
|
|
<&pericfg CLK_PERI_USB_SLV>;
|
|
clock-names = "main","mcu","univpll";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy0: t-phy@11210000 {
|
|
compatible = "mediatek,mt2701-tphy",
|
|
"mediatek,generic-tphy-v1";
|
|
reg = <0 0x11210000 0 0x0800>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "okay";
|
|
|
|
u2port2: usb-phy@1a1c4800 {
|
|
reg = <0 0x11210800 0 0x0100>;
|
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
eth: ethernet@1b100000 {
|
|
compatible = "mediatek,mt2701-eth", "syscon";
|
|
reg = <0 0x1b100000 0 0x20000>;
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<ðsys CLK_ETHSYS_ESW>,
|
|
<ðsys CLK_ETHSYS_GP1>,
|
|
<ðsys CLK_ETHSYS_GP2>,
|
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
|
resets = <ðsys MT2701_ETHSYS_FE_RST>,
|
|
<ðsys MT2701_ETHSYS_GMAC_RST>,
|
|
<ðsys MT2701_ETHSYS_PPE_RST>;
|
|
reset-names = "fe", "gmac", "ppe";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,pctl = <&syscfg_pctl_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bdpsys: syscon@1c000000 {
|
|
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
|
reg = <0 0x1c000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|