0509666660
On each context switch we save the FPU registers on stack of old process and restore FPU registers from the stack of new one. That allows us to avoid doing that each time we enter/leave the kernel mode; however, that can get suboptimal in some cases. For one thing, we don't need to bother saving anything for kernel threads. For another, if between entering and leaving the kernel a thread gives CPU up more than once, it will do useless work, saving the same values every time, only to discard the saved copy as soon as it returns from switch_to(). Alternative solution: * move the array we save into from switch_stack to thread_info * have a (thread-synchronous) flag set when we save them * have another flag set when they should be restored on return to userland. * do *NOT* save/restore them in do_switch_stack()/undo_switch_stack(). * restore on the exit to user mode if the restore flag had been set. Clear both flags. * on context switch, entry to fork/clone/vfork, before entry into do_signal() and on entry into straced syscall save the registers and set the 'saved' flag unless it had been already set. * on context switch set the 'restore' flag as well. * have copy_thread() set both flags for child, so the registers would be restored once the child returns to userland. * use the saved data in setup_sigcontext(); have restore_sigcontext() set both flags and copy from sigframe to save area. * teach ptrace to look for FPU registers in thread_info instead of switch_stack. * teach isolated accesses to FPU registers (rdfpcr, wrfpcr, etc.) to check the 'saved' flag (under preempt_disable()) and work with the save area if it's been set; if 'saved' flag is found upon write access, set 'restore' flag as well. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Matt Turner <mattst88@gmail.com>
90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ALPHA_FPU_H
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#define __ASM_ALPHA_FPU_H
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#include <asm/special_insns.h>
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#include <uapi/asm/fpu.h>
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/* The following two functions don't need trapb/excb instructions
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around the mf_fpcr/mt_fpcr instructions because (a) the kernel
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never generates arithmetic faults and (b) call_pal instructions
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are implied trap barriers. */
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static inline unsigned long
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rdfpcr(void)
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{
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unsigned long tmp, ret;
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preempt_disable();
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if (current_thread_info()->status & TS_SAVED_FP) {
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ret = current_thread_info()->fp[31];
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} else {
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#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
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__asm__ __volatile__ (
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"ftoit $f0,%0\n\t"
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"mf_fpcr $f0\n\t"
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"ftoit $f0,%1\n\t"
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"itoft %0,$f0"
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: "=r"(tmp), "=r"(ret));
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#else
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__asm__ __volatile__ (
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"stt $f0,%0\n\t"
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"mf_fpcr $f0\n\t"
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"stt $f0,%1\n\t"
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"ldt $f0,%0"
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: "=m"(tmp), "=m"(ret));
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#endif
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}
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preempt_enable();
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return ret;
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}
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static inline void
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wrfpcr(unsigned long val)
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{
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unsigned long tmp;
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preempt_disable();
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if (current_thread_info()->status & TS_SAVED_FP) {
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current_thread_info()->status |= TS_RESTORE_FP;
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current_thread_info()->fp[31] = val;
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} else {
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#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
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__asm__ __volatile__ (
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"ftoit $f0,%0\n\t"
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"itoft %1,$f0\n\t"
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"mt_fpcr $f0\n\t"
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"itoft %0,$f0"
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: "=&r"(tmp) : "r"(val));
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#else
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__asm__ __volatile__ (
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"stt $f0,%0\n\t"
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"ldt $f0,%1\n\t"
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"mt_fpcr $f0\n\t"
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"ldt $f0,%0"
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: "=m"(tmp) : "m"(val));
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#endif
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}
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preempt_enable();
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}
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static inline unsigned long
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swcr_update_status(unsigned long swcr, unsigned long fpcr)
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{
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/* EV6 implements most of the bits in hardware. Collect
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the acrued exception bits from the real fpcr. */
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if (implver() == IMPLVER_EV6) {
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swcr &= ~IEEE_STATUS_MASK;
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swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
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}
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return swcr;
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}
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extern unsigned long alpha_read_fp_reg (unsigned long reg);
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extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
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extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
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extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
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#endif /* __ASM_ALPHA_FPU_H */
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