f4c5358253
The reset signal needs to be deasserted before operation of sp805 module. Document in the binding. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20240221-hisi-wdt-v3-2-9642613dc2e6@outlook.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM AMBA Primecell SP805 Watchdog
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maintainers:
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- Viresh Kumar <vireshk@kernel.org>
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description: |+
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The Arm SP805 IP implements a watchdog device, which triggers an interrupt
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after a configurable time period. If that interrupt has not been serviced
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when the next interrupt would be triggered, the reset signal is asserted.
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allOf:
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- $ref: /schemas/watchdog/watchdog.yaml#
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# Need a custom select here or 'arm,primecell' will match on lots of nodes
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select:
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properties:
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compatible:
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contains:
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const: arm,sp805
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: arm,sp805
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- const: arm,primecell
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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clocks:
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description: |
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Clocks driving the watchdog timer hardware. The first clock is used
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for the actual watchdog counter. The second clock drives the register
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interface.
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maxItems: 2
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clock-names:
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items:
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- const: wdog_clk
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- const: apb_pclk
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resets:
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maxItems: 1
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description: WDOGRESn input reset signal for sp805 module.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wdt_clk>, <&apb_pclk>;
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clock-names = "wdog_clk", "apb_pclk";
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resets = <&wdt_rst>;
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};
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