6402eb802d
Document the General Timer Module (a.k.a OSTM) block on Renesas RZ/V2H(P)
("R9A09G057") SoC, which is identical to the one found on the RZ/A1H and
RZ/G2L SoCs. Add the "renesas,r9a09g057-ostm" compatible string for the
RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240322151219.885832-2-prabhakar.mahadev-lad.rj@bp.renesas.com
80 lines
1.8 KiB
YAML
80 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas OS Timer (OSTM)
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maintainers:
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- Chris Brandt <chris.brandt@renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
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can operate in either interval count down timer or free-running compare match
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mode.
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Channels are independent from each other.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r7s72100-ostm # RZ/A1H
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- renesas,r7s9210-ostm # RZ/A2M
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- renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
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- renesas,r9a07g044-ostm # RZ/G2{L,LC}
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- renesas,r9a07g054-ostm # RZ/V2L
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- renesas,r9a09g057-ostm # RZ/V2H(P)
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- const: renesas,ostm # Generic
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- power-domains
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if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a07g043-ostm
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- renesas,r9a07g044-ostm
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- renesas,r9a07g054-ostm
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- renesas,r9a09g057-ostm
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then:
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required:
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r7s72100-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ostm0: timer@fcfec000 {
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compatible = "renesas,r7s72100-ostm", "renesas,ostm";
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reg = <0xfcfec000 0x30>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
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clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
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power-domains = <&cpg_clocks>;
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};
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