adc14d44d7
Add definition for j784s4-pci-ep and j784s4-pci-host devices along with schema checks for num-lanes. Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-3-s-vadapalli@ti.com Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
144 lines
3.1 KiB
YAML
144 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: TI J721E PCI EP (PCIe Wrapper)
|
|
|
|
maintainers:
|
|
- Kishon Vijay Abraham I <kishon@ti.com>
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- const: ti,j721e-pcie-ep
|
|
- const: ti,j784s4-pcie-ep
|
|
- description: PCIe EP controller in AM64
|
|
items:
|
|
- const: ti,am64-pcie-ep
|
|
- const: ti,j721e-pcie-ep
|
|
- description: PCIe EP controller in J7200
|
|
items:
|
|
- const: ti,j7200-pcie-ep
|
|
- const: ti,j721e-pcie-ep
|
|
|
|
reg:
|
|
maxItems: 4
|
|
|
|
reg-names:
|
|
items:
|
|
- const: intd_cfg
|
|
- const: user_cfg
|
|
- const: reg
|
|
- const: mem
|
|
|
|
ti,syscon-pcie-ctrl:
|
|
$ref: /schemas/types.yaml#/definitions/phandle-array
|
|
items:
|
|
- items:
|
|
- description: Phandle to the SYSCON entry
|
|
- description: pcie_ctrl register offset within SYSCON
|
|
description: Specifier for configuring PCIe mode and link speed.
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
description: clock-specifier to represent input to the PCIe
|
|
|
|
clock-names:
|
|
items:
|
|
- const: fck
|
|
|
|
dma-coherent:
|
|
description: Indicates that the PCIe IP block can ensure the coherency
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
interrupt-names:
|
|
items:
|
|
- const: link_state
|
|
|
|
allOf:
|
|
- $ref: cdns-pcie-ep.yaml#
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- ti,am64-pcie-ep
|
|
then:
|
|
properties:
|
|
num-lanes:
|
|
const: 1
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- ti,j7200-pcie-ep
|
|
- ti,j721e-pcie-ep
|
|
then:
|
|
properties:
|
|
num-lanes:
|
|
minimum: 1
|
|
maximum: 2
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- ti,j784s4-pcie-ep
|
|
then:
|
|
properties:
|
|
num-lanes:
|
|
minimum: 1
|
|
maximum: 4
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- reg-names
|
|
- ti,syscon-pcie-ctrl
|
|
- max-link-speed
|
|
- num-lanes
|
|
- power-domains
|
|
- clocks
|
|
- clock-names
|
|
- max-functions
|
|
- phys
|
|
- phy-names
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
|
|
|
bus {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
pcie0_ep: pcie-ep@d000000 {
|
|
compatible = "ti,j721e-pcie-ep";
|
|
reg = <0x00 0x02900000 0x00 0x1000>,
|
|
<0x00 0x02907000 0x00 0x400>,
|
|
<0x00 0x0d000000 0x00 0x00800000>,
|
|
<0x00 0x10000000 0x00 0x08000000>;
|
|
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
|
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
|
|
max-link-speed = <3>;
|
|
num-lanes = <2>;
|
|
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 239 1>;
|
|
clock-names = "fck";
|
|
max-functions = /bits/ 8 <6>;
|
|
dma-coherent;
|
|
phys = <&serdes0_pcie_link>;
|
|
phy-names = "pcie-phy";
|
|
};
|
|
};
|