5db62b7d3c
dtschema package with core schemas deprecated pci-bus.yaml schema in favor of pci-host-bridge.yaml. Update all bindings to use the latter one. The difference between pci-bus.yaml and pci-host-bridge.yaml is only in lack of "reg" property defined by the latter, which should not have any effect here, because all these bindings define the "reg". The change is therefore quite trivial, however it requires dtschema package v2024.02 or newer. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # Renesas Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
127 lines
3.0 KiB
YAML
127 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI AM65 PCI Host
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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enum:
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- ti,am654-pcie-rc
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- ti,keystone-pcie
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: app
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- const: dbics
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- const: config
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- const: atu
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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ti,syscon-pcie-id:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the SYSCON entry
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- description: pcie_device_id register offset within SYSCON
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description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
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ti,syscon-pcie-mode:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the SYSCON entry
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- description: pcie_ctrl register offset within SYSCON
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description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
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msi-map: true
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dma-coherent: true
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num-viewport:
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$ref: /schemas/types.yaml#/definitions/uint32
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phys:
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description: per-lane PHYs
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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pattern: '^pcie-phy[0-1]$'
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required:
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- compatible
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- reg
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- reg-names
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- max-link-speed
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- ti,syscon-pcie-id
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- ti,syscon-pcie-mode
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- ranges
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if:
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properties:
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compatible:
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enum:
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- ti,am654-pcie-rc
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then:
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required:
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- dma-coherent
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- power-domains
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- msi-map
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- num-viewport
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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pcie0_rc: pcie@5500000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x5500000 0x1000>,
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<0x5501000 0x1000>,
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<0x10000000 0x2000>,
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<0x5506000 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
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<0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&scm_conf 0x0210>;
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ti,syscon-pcie-mode = <&scm_conf 0x4060>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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device_type = "pci";
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num-lanes = <1>;
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phys = <&serdes0 PHY_TYPE_PCIE 0>;
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phy-names = "pcie-phy0";
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};
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