52d06636a4
Properties with GPIOs should define number of actual GPIOs, so add
missing maxItems to ep-gpios. Otherwise multiple GPIOs could be
provided which is not a true hardware description.
Fixes: aa222f9311 ("dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema")
Link: https://lore.kernel.org/linux-pci/20240401100058.15749-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
134 lines
3.6 KiB
YAML
134 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip AXI PCIe Root Port Bridge Host
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- $ref: rockchip,rk3399-pcie-common.yaml#
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properties:
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compatible:
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const: rockchip,rk3399-pcie
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reg: true
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reg-names:
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items:
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- const: axi-base
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- const: apb-base
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: sys
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- const: legacy
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- const: client
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aspm-no-l0s:
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description: This property is needed if using 24MHz OSC for RC's PHY.
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ep-gpios:
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maxItems: 1
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description: pre-reset GPIO
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vpcie12v-supply:
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description: The 12v regulator to use for PCIe.
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vpcie3v3-supply:
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description: The 3.3v regulator to use for PCIe.
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vpcie1v8-supply:
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description: The 1.8v regulator to use for PCIe.
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vpcie0v9-supply:
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description: The 0.9v regulator to use for PCIe.
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interrupt-controller:
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type: object
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additionalProperties: false
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properties:
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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required:
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- ranges
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- "#interrupt-cells"
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- interrupts
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- interrupt-controller
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- interrupt-map
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- interrupt-map-mask
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- msi-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/rk3399-cru.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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num-lanes = <4>;
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msi-map = <0x0 &its 0x0 0x1000>;
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reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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/* deprecated legacy PHY model */
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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...
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