21a2960d5e
Update the example in the documentation to a valid example. Address for mem-base was invalid, it pointed to address 0x8000'0000 which is the upper region of the DDR which is not necessarily populated depending on the board. This address should point to the base of the memory window region of the controller which is 0xfa00'0000. Add missing pinctrl. Link: https://lore.kernel.org/r/20230418074700.1083505-7-rick.wertenbroek@gmail.com Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
71 lines
2.0 KiB
YAML
71 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip AXI PCIe Endpoint
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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allOf:
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- $ref: /schemas/pci/pci-ep.yaml#
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- $ref: rockchip,rk3399-pcie-common.yaml#
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properties:
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compatible:
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const: rockchip,rk3399-pcie-ep
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reg: true
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reg-names:
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items:
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- const: apb-base
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- const: mem-base
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rockchip,max-outbound-regions:
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description: Maximum number of outbound regions
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 32
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default: 32
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required:
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- rockchip,max-outbound-regions
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/rk3399-cru.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-ep@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
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reg-names = "apb-base", "mem-base";
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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max-functions = /bits/ 8 <8>;
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num-lanes = <4>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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rockchip,max-outbound-regions = <16>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreqnb_cpm>;
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};
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};
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...
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