ada94d0062
'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-4-263a385fbbcb@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
285 lines
7.1 KiB
YAML
285 lines
7.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCIe Endpoint Controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,sa8775p-pcie-ep
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- qcom,sdx55-pcie-ep
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- qcom,sm8450-pcie-ep
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- items:
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- const: qcom,sdx65-pcie-ep
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- const: qcom,sdx55-pcie-ep
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reg:
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minItems: 6
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items:
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- description: Qualcomm-specific PARF configuration registers
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- description: DesignWare PCIe registers
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- description: External local bus interface registers
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- description: Address Translation Unit (ATU) registers
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- description: Memory region used to map remote RC address space
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- description: BAR memory region
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- description: DMA register space
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reg-names:
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minItems: 6
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: atu
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- const: addr_space
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- const: mmio
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- const: dma
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clocks:
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minItems: 5
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maxItems: 8
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clock-names:
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minItems: 5
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maxItems: 8
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qcom,perst-regs:
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description: Reference to a syscon representing TCSR followed by the two
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offsets within syscon for Perst enable and Perst separation
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enable registers
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Syscon to TCSR system registers
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- description: Perst enable offset
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- description: Perst separation enable offset
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interrupts:
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minItems: 2
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items:
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- description: PCIe Global interrupt
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- description: PCIe Doorbell interrupt
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- description: DMA interrupt
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interrupt-names:
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minItems: 2
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items:
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- const: global
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- const: doorbell
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- const: dma
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reset-gpios:
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description: GPIO used as PERST# input signal
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maxItems: 1
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wake-gpios:
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description: GPIO used as WAKE# output signal
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maxItems: 1
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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resets:
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maxItems: 1
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reset-names:
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const: core
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power-domains:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pciephy
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num-lanes:
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default: 2
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reset-gpios
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- interconnects
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- interconnect-names
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- resets
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- reset-names
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- power-domains
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allOf:
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- $ref: pci-ep.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdx55-pcie-ep
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then:
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properties:
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reg:
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maxItems: 6
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reg-names:
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maxItems: 6
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe Sleep clock
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- description: PCIe Reference clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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- const: sleep
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- const: ref
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interrupts:
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maxItems: 2
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interrupt-names:
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-pcie-ep
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then:
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properties:
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reg:
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maxItems: 6
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reg-names:
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maxItems: 6
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe Reference clock
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- description: PCIe DDRSS SF TBU clock
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- description: PCIe AGGRE NOC AXI clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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- const: ref
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- const: ddrss_sf_tbu
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- const: aggre_noc_axi
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interrupts:
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maxItems: 2
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interrupt-names:
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sa8775p-pcie-ep
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then:
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properties:
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reg:
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minItems: 7
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maxItems: 7
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reg-names:
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minItems: 7
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maxItems: 7
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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interrupts:
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minItems: 3
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maxItems: 3
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interrupt-names:
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minItems: 3
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maxItems: 3
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sdx55.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@1c00000 {
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compatible = "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xc8>,
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<0x40001000 0x1000>,
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<0x40002000 0x1000>,
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<0x01c03000 0x3000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio";
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clocks = <&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>;
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clock-names = "aux", "cfg", "bus_master", "bus_slave",
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"slave_q2a", "sleep", "ref";
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qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell";
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interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
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<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie0_lane>;
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phy-names = "pciephy";
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max-link-speed = <3>;
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num-lanes = <2>;
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linux,pci-domain = <0>;
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};
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